ISL1220IUZ-T Intersil, ISL1220IUZ-T Datasheet - Page 4

• Manufacturer Part Number: ISL1220IUZ-T
• Description: IC RTC LP BATT BACK SRAM 10MSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Alarmr

Specifications of ISL1220IUZ-T

• Memory Size: 8B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL1220IUZ-TTR

Serial Interface Specifications
NOTES:
Hysteresis SDA and SCL Input Buffer
SYMBOL
2. IRQ and F
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the V
5. Typical values are for T = 25°C and 3.3V supply voltage.
6. These are I
7. A write to register 08h should only be done if V
t
t
t
t
t
t
HD:STO
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
t
t
Cpin
t
f
HIGH
V
LOW
Rpu
V
SCL
t
BUF
t
t
Cb
DH
AA
t
t
IN
OL
R
IH
F
SDA and SCL Input Buffer HIGH
Voltage
Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 3mA
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP condItion Hold Time
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
SDA and SCL Bus Pull-up Resistor
Off-chip
OUT
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
Inactive.
PARAMETER
4
Over the recommended operating conditions unless otherwise specified. (Continued)
DD SR-
T
V
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
SDA exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
during the following START condition.
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge. Both
crossing 70% of V
From SDA falling edge crossing 30% of V
to SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of
V
From SCL falling edge crossing 30% of V
to SDA entering the 30% to 70% of V
window.
From SCL rising edge crossing 70% of V
to SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge.
Both crossing 70% of V
From SCL falling edge crossing 30% of V
until SDA enters the 30% to 70% of V
window.
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
Maximum is determined by t
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
DD
A
OUT
DD
= 25°C, f = 1MHz, V
> V
specification must be followed.
= 0V
BAT
, otherwise the device will be unable to communicate using I
TEST CONDITIONS
ISL1220
DD
.
DD
DD
DD
DD
DD
DD
DD
.
= 5V, V
during a STOP
R
crossing.
crossing.
and t
DD
IN
window.
DD
F
DD
.
= 0V,
DD
DD
DD
DD
, until
DD
DD
DD
DD
DD
.
.
,
,
0.1 x Cb
0.1 x Cb
0.05 x
1300
1300
0.7 x
V
V
20 +
20 +
MIN
600
600
600
100
600
600
10
DD
DD
0
0
0
1
(Note 5)
TYP
V
MAX
400
900
900
300
300
400
DD
0.3
0.4
10
50
2
C.
+
UNITS
kHz
pF
pF
kΩ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
June 22, 2006
NOTES
FN6315.0
6
6
6
6