AD8389ACPZ Analog Devices Inc, AD8389ACPZ Datasheet - Page 5

• Manufacturer Part Number: AD8389ACPZ
• Description: IC TRPL DELAY LOCK LOOP 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Delayed, Locked Loopr

Specifications of AD8389ACPZ

• Frequency: 85MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 11mA
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Mnemonic
AVDD, DRVDD
AVSS, DRVSS
CLK
COMPEDGE
SLOW
DXI
CLXI
ENBX(1–4)I
MONITxI
DXxO
CLXxO
ENBX(1–4)xO
VCONTx
Function
Power Supply
Ground
Clock
Edge Select
Delay Select
Reference Input
Input
Inputs
Feedback Inputs
Delayed Outputs
Delayed Outputs
Delayed Outputs
Control Voltage
MONITRI
MONITGI
MONITBI
VCONTR
VCONTG
VCONTB
NC =
NO CONNECT
AVDD
AVDD
AVSS
AVSS
AVSS
AVSS
Description
Power Supply.
Ground.
Clock Input. Active edge is the rising edge.
When set HIGH, the phase detector compares the falling edge of DXIN with the rising edge of
MONITxI. When set LOW, the phase detector compares the rising edge of DXIN with the falling
edge of MONITxI.
When set HIGH and COMPEDGE = HIGH, the delay between the falling edges of DXI and the
rising edges of MONITI is maintained at 9/(f
COMPEDGE = LOW. When set LOW and COMPEDGE = HIGH, the delay between the falling edges
of DXI and the rising edges of MONITI is maintained at 15/(f
32/(f
LCD Timing Input from the Image Processor. Used as the input to all phase detectors.
LCD Timing Input from the Image Processor.
LCD Timing Inputs from the Image Processor.
Inputs from the LCD. Used as the feedback input to each phase detector. When the AD8389
forms part of a closed loop, it maintains a constant delay between the DXI input and this
reference input pin.
200 pF capacitors connected between these pins and the AVSS plane are required for proper
operation of the internal charge pump.
Figure 3. 48-Lead LFCSP, 7 mm × 7 mm Pin Configuration
10
11
12
1
2
3
4
5
6
7
8
9
CLK
) + t
4
with COMPEDGE = LOW.
PIN 1
INDICATOR
Rev. 0 | Page 5 of 12
48-LEAD LFCSP
(Not to Scale)
7mm × 7mm
AD8389
TOP VIEW
CLK
) + t
36
35
34
33
32
31
30
29
28
27
26
25
DXRO
ENBX1RO
ENBX2RO
ENBX3RO
ENBX4RO
CLXRO
DXGO
ENBX1GO
ENBX2GO
ENBX3GO
ENBX4GO
CLXGO
4
. The delay is maintained at 26/(f
CLK
) + t
4
. The delay is maintained at
CLK
) + t
AD8389
4
when