DS1077LU-66 Maxim Integrated Products, DS1077LU-66 Datasheet - Page 6

• Manufacturer Part Number: DS1077LU-66
• Description: ECONOSCILL 2WIRE 66MHZ 8-USOP
• Manufacturer: Maxim Integrated Products
• Series: EconOscillator™r
• Type: Oscillator, Fixed Frequency, Dualr

Specifications of DS1077LU-66

• Mfg Application Notes: DS1077L Application Notes
• Frequency: 66MHz
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Supply: 30mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Count: -

EN0 (bit)
If EN0 = 1 and PDN0 = 0, the CTRL0 pin functions as an output enable for OUT0, the frequency of the
output is determined by the SEL0 bit.
If PDN0 = 1, the EN0 bit is ignored, CTRL0 will function as a power-down, output OUT0 will always be
enabled on power-up, and its frequency is determined by the SEL0 bit.
If EN0 = 0, the function of CTRL0 is determined by the SEL0 and PDN0 bits. (See Table 1.)
SEL0
If SEL0 = 1 and EN0 = PDN0 = 0, the CTRL0 pin determines the state of the MUX, (i.e., the output
frequency of OUT0).
If CTRL0 = 0, the output will be the master clock frequency.
If CTRL0 = 1, the output will be the output frequency of the M prescaler.
If either EN0 or PDN0 = 1, then SEL0 determines the frequency of OUT0 when it is enabled.
If SEL0 = 0, the output will be the master clock frequency.
If SEL0 = 1, the output will be the output frequency of the M prescaler. (See Table 1.)
PDN0
This bit (if set to 1) causes CTRL0 to perform a power-down function, regardless of the setting of the
other bits.
If PDN0 = 0, the function of CTRL0 is determined by the values of EN0 and SEL0.
NOTE:
When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case where all
the OUT0 circuitry is disabled even when the device is powered up. This feature can be used to save
power when OUT0 is not used. (See Table 1.)
PDN1
If PDN1 = 1, CTRL1 will function as a power-down.
If PDN1 = 0, CTRL1 functions as an output enable for OUT1 only. (See Table 2.)
NOTES (ON OUTPUT ENABLE AND POWER-DOWN):
1. Both enables are “smart” and wait for the output to be low before going to Hi-Z.
2. Power-down sequence first disables both outputs before powering down the device.
3. On power-up, the outputs are disabled until the clock has stabilized (~8000 cycles).
4. The device cannot be programmed in power-down mode.
5. A power-down command must persist for at least 2 cycles of the lowest output frequency plus 10µs.
DIV WORD
N
These ten bits determine the value of the programmable divider (N). The range of divisor values is from 2
to 1025, and is equal to the programmed value of N plus 2. (See Table 5.)
MSB
N9
N8
N7
N6
first data byte
N5
N4
N3
N2
LSB MSB
6 of 21
N1
N0
X
second data byte
X
(Default PDN0 = 0)
X
(Default PDN1 = 0)
(Default SEL0 = 1)
(Default EN0 = 1)
X
X
LSB
X