DS1045S-3 Maxim Integrated Products, DS1045S-3 Datasheet - Page 2

• Manufacturer Part Number: DS1045S-3
• Description: DELAY LINE 16TAP 3NS 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS1045S-3

• Number Of Taps/steps: 16
• Function: Programmable
• Delay To 1st Tap: 9nS
• Tap Increment: 3nS
• Available Total Delays: 54ns
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Independent Delays: -

PARALLEL PROGRAMMING
Parallel programming of the DS1045 is accomplished via the set of parallel inputs A0-A3 and B0-B3 as
shown in Figure 1. Parallel input A0-A3 and B0-B3 accept TTL levels and are used to set the delay
values of outputs OUTA and OUTB, respectively. Sixteen possible delay values between the minimum
9ns delay and the maximum delay of the DS1045-x device version can be selected using the parallel
programming inputs A0-A3 or B0-B3 (see Table 2, “Delay vs. Programmed Input”). For example, the
DS1045-3 outputs OUTA or OUTB and can be programmed to produce 16 possible delays between the
9ns (minimum) and the 54ns (maximum) in 3ns increment levels.
For applications that do not require frequent reprogramming, the parallel inputs can be set using fixed
logic levels, as would be produced by jumpers, DIP switches, or TTL levels as produced by computer
systems. Maximum flexibility in parallel programming can be achieved when inputs are set by computer-
generated data. By using the enable input pins for each respective programmed output and observing the
input setup (t
pins,
programmed delay value, a settling time (t
reliably produced. Since the DS1045 is a CMOS design, undefined input pins should be connected to well
defined logic levels and not left floating.
PART NUMBER TABLE Table 1
NOTE:
Additional delay step times are available from Dallas Semiconductor by special order. Consult factory for
availability.
BLOCK DIAGRAM Figure 1
PART NUMBER
EA
DS1045-3
DS1045-4
DS1045-5
and
DSE
EB
) and hold time (t
, are not used to latch data, they should be set to a logic level 1. After each change in the
STEP ZERO DELAY
DHE
9 =1ns
9 =1ns
9 =1ns
) requirements, data can be latched on an 8-bit bus. If the enable
EDV
) or (t
2 of 6
PDV
MAX DELAY TIME
) is required before the delayed output signal is
54ns
69ns
84ns
TOLERANCE
MAX DELAY
2.5ns
3.3ns
4.1ns
DS1045