DS1010S-100 Maxim Integrated Products, DS1010S-100 Datasheet - Page 5
![no-image](/images/manufacturer_photos/0/4/417/maxim_integrated_products_sml.jpg)
DS1010S-100
Manufacturer Part Number
DS1010S-100
Description
DELAY LINE 10TAP 100NS 16-SOIC
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1010S-500.pdf
(6 pages)
Specifications of DS1010S-100
Number Of Taps/steps
10
Function
Tapped
Delay To 1st Tap
10nS
Tap Increment
10nS
Available Total Delays
100ns
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Independent Delays
-
Other names
DS1010S100
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS1010S-100
Manufacturer:
GENESIS
Quantity:
91
Part Number:
DS1010S-100
Manufacturer:
DALLAS
Quantity:
20 000
TEST CIRCUIT Figure 3
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
input pulse.
t
input pulse.
t
pulse and the 1.5V point on the leading edge of any tap output pulse.
t
pulse and the 1.5V point on the trailing edge of any tap output pulse.
WI
RISE
FALL
PLH
PHL
(Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
(Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
(Time Delay Rising): The elapsed time between the 1.5V point on the leading edge of the input
(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
5 of 6
DS1010