DS1023S-50/T&R Maxim Integrated Products, DS1023S-50/T&R Datasheet - Page 4

• Manufacturer Part Number: DS1023S-50/T&R
• Description: DELAY PROG 8-BIT 0.50NS 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS1023S-50/T&R

• Number Of Taps/steps: 256
• Function: 1-Shot
• Delay To 1st Tap: 16.5nS
• Tap Increment: 0.5nS
• Available Total Delays: 127.5ns
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Independent Delays: -

DS1023
For highest accuracy it is strongly recommended that the reference delay is used. Variations in input
voltage levels and transition times can significantly alter the measured delay from input to output. This
effect is totally removed if the reference delay output is used. Furthermore, adverse effects on step zero
delay caused by process temperature coefficients are also cancelled out.
INPUT PULSE DURATION
The internal architecture of the DS1023 allows the output delay time to be considerably longer than the
input pulse width (see ac specifications). This feature is useful in many applications, in particular clock
phase control where delays up to and beyond one full clock period can be achieved.
MODE SELECT
The DS1023 has four possible output functions but only two output pins. The functionality of the two
output pins is determined by the Mode Select (MS) pin.
MS = 0 Figure 3
Output Function
Name
Pin Number
Reference Output
REF
9
Delayed Output
OUT
15
OUT is a copy of the input waveform that is delayed by an amount set by the programmed values (Table
1). A programmed value of zero will still result in a non-zero delay as indicated in the Step Zero delay
specification. The signal on OUT is the same polarity as the input.
REF is a fixed reference delay. It also is a copy of the input waveform but the delay interval is fixed to a
value approximately equal to the Step Zero Value of the device (as shown in the Reference Delay
specification). In fact the device is trimmed to ensure that the Reference Delay is always slightly longer
than the Step Zero Value (by 1.5 ns typically).
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