DS1124U-25+T Maxim Integrated Products, DS1124U-25+T Datasheet - Page 7

• Manufacturer Part Number: DS1124U-25+T
• Description: IC TIMING ELEMENT PROG 10-USOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1124U-25+T

• Number Of Taps/steps: 256
• Function: Programmable
• Delay To 1st Tap: 20nS
• Tap Increment: 0.25nS
• Available Total Delays: 83.75ns
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Independent Delays: -

Figure 3. Serial Interface Timing Diagram
Figure 4C shows how to cascade multiple DS1124s onto
the same 3-wire bus. One important detail of writing
software for cascaded 3-wire devices is that all the
devices on the bus must be written to or read from
during each read or write cycle. Attempting to write to
only the first device (U1) would cause the data stored in
U1 to be shifted to U2, U2’s data would be shifted to U3,
etc. As shown, the microprocessor would have to shift
24 bits during each read or write cycle to avoid inadver-
tently changing the settings in any of the 3-wire devices.
Also note that the feedback resistor or a separate input
(not shown) can still be used to read the 3-wire device
settings when multiple devices are cascaded.
OUTPUT
ENABLE
CLOCK
SERIAL
SERIAL
DELAY
INPUT
(CLK)
TIME
(D)
(Q)
(E)
_______________________________________________________________________________________
t
EQV
t
ES
t
DSC
NEW BIT 7
OLD BIT 7
t
t
CQV
CW
t
DHC
PREVIOUS VALUE
NEW BIT 6
OLD BIT 6
t
CW
t
EW
5.0V 8-Bit Programmable
Integral nonlinearity (INL) is defined as the deviation
from a straight line response drawn between the mea-
sured step zero delay (t
delay (t
shows INL’s effect on delay performance graphically.
To achieve the best results when using the DS1124,
decouple the power supply with a 0.01µF and a 0.1µF
capacitor. Use high-quality, ceramic, surface mount
capacitors, and mount the capacitors as close as possi-
ble to the V
lead inductance. The DS1124 may not perform as speci-
fied if good decoupling practices are not followed.
t
CQX
D255
CC
) with respect to the step 0 delay. Figure 5
OLD BIT 0
and GND pins of the DS1124 to minimize
NEW BIT 0
Timing Element
Application Information
Power-Supply Decoupling
t
EH
D0
t
EDX
) and the measured step 255
Integral Nonlinearity
t
EDV
t
EQZ
NEW VALUE
7