SI4133T-GM Silicon Laboratories Inc, SI4133T-GM Datasheet - Page 22

• Manufacturer Part Number: SI4133T-GM
• Description: IC RF SYNTHESIZER DUAL 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4133T-GM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Aero
4.3. Frequency Synthesizer
The Si4133T dual frequency synthesizer is a monolithic
CMOS integrated circuit that performs IF and RF
synthesis. Two complete PLLs are integrated including
VCOs, varactors, resonators, loop filters, reference and
VCO dividers, and phase detectors. Differential outputs
for the IF and RF PLLs are provided for direct
connection to the Si4200 transceiver IC. The RF PLL
uses two multiplexed VCOs. The RF1 VCO is used for
Receive mode, and the RF2 VCO is used for Transmit
mode. The IF PLL is used only during Transmit mode.
The IF and RF output frequencies are set by
programming the N-Divider registers, N
N
or RF2 automatically selects the proper VCO. The
output frequency of each PLL is as follows:
The DIV2 bit in Register 31h controls a programmable
divider at the XIN pin to allow either a 13 or 26 MHz
reference frequency. For receive mode, the RF1 PLL
phase detector update rate (f
to f
to f
For transmit mode, the RF2 and IF PLL phase detector
update rates are always f
22
IF
. Programming the N-Divider register for either RF1
φ
φ
= 100 kHz for DCS 1800 or PCS 1900 bands, and
= 200 kHz for GSM 850 and E-GSM 900 bands.
SCLK
PDN
SDO
SEN
XIN
SDI
CONTROL
POWER
SERIAL
f
OUT
I/O
Figure 15. Si4133T Frequency Synthesizer Block Diagram
φ
=
= 200 kHz.
÷1, 2
DIV2
N f
φ
) should be programmed
×
PDIB
PDRB
SDOSEL[4:0]
φ
RFUP
÷130
÷65,
RF1
, N
TUNE
TUNE
SELF
SELF
RF2
DET
DET
φ
φ
, and
Rev. 1.4
RFLA, RFLB
RF PLL
IF PLL
IFLA
IFLB
N
N
RFLC, RFLD
RF1
RF2
N
IF
[15:0]
[15:0]
[15:0]
÷N
÷N
RF1
RF2
Si4133T
RFLOP
RFLON
IFLOP
IFLON