PI6C3Q993-5QE Pericom Semiconductor, PI6C3Q993-5QE Datasheet - Page 3

• Manufacturer Part Number: PI6C3Q993-5QE
• Description: IC PROG PLL CLOCK DRIVER 28-QSOP
• Manufacturer: Pericom Semiconductor
• Series: SuperClock®r
• Type: PLL Clock Driverr

Specifications of PI6C3Q993-5QE

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 85MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• Frequency-max: 85MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Programmable Skew
Output skew with respect to the REF input is adjustable to compen-
sate for PCB trace delays, backplane propagation delays or to
accommodate requirements for special timing relationships between
clocked components. Skew is selectable as a multiple of time units
- t
9 skew configurations available for each output pair. These configu-
rations are choosen by the nF[1:0] control pins. In order to minimize
the number of control pins, 3-level inputs (HIGH-MID-LOW) are
used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew
is not a requirement, the control pins can be left open for the zero skew
default setting. The skew selection Table (Table 3) shows how to
select specific skew taps by using the nF[1:0] control pins.
Notes:
2. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
3. The level on FS is determined by the nominal operating frequency of the V
4. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then
S
i T
V
M
E
E
E
E
E
E
U
e k
a x
a x
a x
a x
a x
Selecting the appropriate FS value based on input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is
lowest.
frequency appears at 1Q[1:0], 2Q[1:0], and the higher outputs when they are operated in undivided modes. The
frequency appearing at REF and FB inputs are the same as the V
The frequency of the REF and FB inputs are 1/2 or 1/4 the V
multiplication by using a divided output as the FB input.
adjustment range greater. For example if a 4t
–4t
3 and 4 where ±6t
a x
i m
C
a
which is of the order of a nanosecond (see Table 2). There are
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. x
w
m
m
m
m
m
m
g n
U
f
e r
p
p
p
p
p
p
d a
in addition to whatever skew value is programmed for those outputs. Max adjustment range applies to output pairs
d a
09-0003
e l
e l
e l
e l
e l
e l
u
u q
t i n
u j
u j
, 1
, 2
, 3
, 4
, 5
, 6
n e
t s
t s
a c
m
y c
F
F
F
F
F
F
m
N
N
N
N
N
N
e
c l
n e
O
O
O
O
O
O
t n
r
l u
M
M
M
M
M
M
n a
r t
i t a
U
=
=
=
=
=
=
e g
n a
skew adjustment is possible and at the lowest F
n o
5 1
5 2
0 3
0 4
0 5
0 8
e g
F (
t (
) 4 (
M
M
M
M
M
M
N
U
O
Table 2. PLL Programmable Skew Range and Resolution Table
)
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H
H
H
H
H
M
)
z
z
z
z
z
z
2 (
) 3 ,
5 1
U
F
1
t
t
t
U
U
U
S
( /
skewed output is used, all other outputs will be skewed by
±
o t
=
=
=
4 4
±
. 9
±
=
4 1
4
. 1
. 0
. 0
5 3
9 0
F x
L
° 9
%
2 5
1 9
6 7
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N
s n
M
O
W
s n
s n
s n
M
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)
z
CO
frequency when the part is configured for frequency
CO
3.3V Programmable Skew PLL Clock Driver SuperClock
NOM
when the output is connected to FB undivided.
3
External Feedback
By providing external feedback, the PI6C3Q99X family gives users
flexibility with regard to skew adjustment. The FB signal is compared
with the input REF signal at the phase detector in order to drive the
V
down accordingly. An internal loop filter moderates the response of
the V
been chosen to provide minimal jitter (or frequency variation) while
still providing accurate responses to input frequency.
value.
5 2
CO
CO
1
F
t
t
t
t
U
U
U
U
( /
S
±
o t
. Phase differences causes the V
=
=
=
=
6 2
and Time Unit Generator. The V
±
CO
. 9
±
=
3 2
0 6
8
. 1
. 1
. 0
. 0
F x
3 2
° 3
to the phase detector. The loop filter transfer function has
M
%
4 5
8 2
6 9
7 7
N
s n
M
I
O
s n
s n
s n
s n
D
M
H
)
z
0 4
F
1
t
t
t
S
U
U
U
( /
±
o t
=
=
=
6 1
±
±
=
. 9
3 1
7 3
5 8
. 1
. 1
. 0
CO
PI6C3Q991, PI6C3Q993
8 3
F x
H
° 5
6 5
5 2
8 7
CO
%
I
N
s n
M
G
O
s n
s n
s n
M
of the PLL to adjust up or
H
H
)
z
PS8449H
10/27/09
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