MPC9774AE Freescale Semiconductor, MPC9774AE Datasheet - Page 5

• Manufacturer Part Number: MPC9774AE
• Description: IC PLL CLK GENERATOR 1:14 52LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9774AE

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:14
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

a AC characteristics apply for parallel output termination of 50Ω to V
b In bypass mode, the MPC9774 divides the input reference clock.
c The input reference frequency must match the VCO lock range divided by the total feedback divider ratio (FB): f
d Calculation of reference duty cycle limits: DC
e Static phase offset depends on the reference frequency: t
f
g Valid for all outputs at the same fequency.
h I/O jitter for f
i
TIMING SOLUTIONS
Table 8. AC Characteristics (V
f
f
f
t
t
t
t
DC
t
t
t
t
t
t
BW
t
Symbol
REF
VCO
MAX
PW,MIN
R
(∅)
SK(O)
R
PLZ, HZ
PZL
JIT(CC)
JIT(PER)
JIT(∅)
LOCK
the input duty cycle range is 12.5% < DC < 87.5%.
See application section for part-to-part skew calculation.
than 1 s.
-3 dB point of PLL transfer characteristics.
, t
, t
F
F
VCO
Input Reference Frequency
VCO Frequency Range
Output Frequency
Input Reference Pulse Width
CCLKx Input Rise/Fall Time
Propagation Delay (static phase offset)
Output-to-output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle Jitter
Period Jitter
I/O Phase Jitter RMS (1 σ)
PLL Closed Loop Bandwidth
Maximum PLL Lock Time
=400 MHz. See application section for I/O jitter at other frequencies and for a jitter calculation for confidence factors other
Input Reference Frequency in PLL Bypass Mode
f
CCLKx to FB_IN (FB=÷8 and f
g
CC
Characteristics
f
c
= 3.3V ± 5%, T
h
i
d
REF,MIN
e
= t
A
PW,MIN
= 0°C to +70°C)
(∅)
within QC bank
within QA bank
within QB bank
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
REF
÷8 feedback
= +50 ps ± (1÷(120  f
÷12 output
÷16 output
÷24 output
any output
=50 MHz)
⋅ f
÷4 output
÷8 output
FB=÷12
FB=÷16
FB=÷24
FB=÷32
FB=÷48
FB=÷12
FB=÷16
FB=÷24
FB=÷32
FB=÷48
REF
FB=÷8
FB=÷8
TT
5
.
⋅ 100% and DC
b
a
25.0
16.6
12.5
8.33
6.25
4.16
50.0
25.0
16.6
12.5
8.33
-250
Min
200
2.0
0.1
47
REF
REF,MAX
)) for any reference frequency.
0.50 - 1.80
0.30 - 1.00
0.25 - 0.70
0.17 - 0.40
0.12 - 0.30
0.07 - 0.20
Typ
= 100% - DC
50
15.625
31.25
20.83
10.41
125.0
31.25
20.83
+100
Max
62.5
41.6
62.5
41.6
REF, MIN.
250
500
100
125
100
175
1.0
1.0
53
10
10
90
90
15
49
18
22
26
34
10
REF
E.g. at f
=f
MHZ
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
VCO
ms
ns
ns
ps
ps
ps
ps
ps
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
%
÷(M ⋅ VCO_SEL).
REF
MPC9774
PLL locked
PLL bypass
PLL locked
0.8 to 2.0V
PLL locked
0.55 to 2.4V
Condition
MOTOROLA
=62.5 MHz