MPC9658AC Freescale Semiconductor, MPC9658AC Datasheet - Page 9

• Manufacturer Part Number: MPC9658AC
• Description: IC PLL CLK GENERATOR 1:10 32LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9658AC

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: Yes/No
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced Clock Drivers Device Data
Freescale Semiconductor
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
Figure 10. Output-to-Output Skew t
Figure 12. Output Duty Cycle (DC)
Figure 14. Cycle-to-Cycle Jitter
t
T
P
N
T
T
0
N+1
DC = t
t
SK(O)
P
/T
0
T
x 100%
JIT(CC)
= |T
N
SK(O)
Figure 16. Output Transition Time Test
–T
t
N+1
V
V
GND
F
CC
CC
V
V
GND
V
V
GND
|
CC
CC
CC
CC
÷ 2
÷ 2
÷ 2
Reference
PCLK
PCLK
FB_IN
The deviation in t
mean in a random sample of cycles
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
Figure 11. Propagation Delay (t
PCLK
FB_IN
t
R
V
CC
0.55
=3.3 V
2.4
0
T
V
offset) Test Reference
0
PP
for a controlled edge with respect to a T
Figure 15. Period Jitter
= 0.8V
Figure 13. I/O Jitter
t
(PD)
T
JIT(∅)
T
JIT(PER)
(PD)
= |T
, static phase
= |T
0
–T
1
N
mean|
–1/f
MPC9658
0
|
V
V
V
V
GND
CC
CC
CMR =
CC
–1.3V
0
÷ 2
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