SI5320-F-BC Silicon Laboratories Inc, SI5320-F-BC Datasheet - Page 27

• Manufacturer Part Number: SI5320-F-BC
• Description: IC PREC CLOCK MULTIPLIER 63CBGA
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5320-F-BC

• Package / Case: 63-CBGA
• Pll: Yes
• Input: LVTTL
• Output: CML
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 693MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 693MHz
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1141

*Note: The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a
A4–8, B5, B8
D6, D7, E6,
B2, B3, B6,
E7, F3–F7
D3–D5,
B7, C8
E3–E5
Pin #
B1
C1
E8
H4
C2
logic low state if the input is not driven from an external source.
RSVD_GND
CAL_ACTV
RSVD_NC
Pin Name
BWSEL[0]
BWSEL[1]
VALTIME
VSEL33
V
V
DD33
DD25
Table 11. Si5320 Pin Descriptions (Continued)
V
V
I/O
—
—
O
I*
I*
I*
DD
DD
Signal Level
Supply
Supply
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Rev. 2.3
Bandwidth Select.
BWSEL[1:0] pins set the bandwidth of the loop filter
within the DSPLL to 6400, 3200, 1600, or 800 Hz as
indicated below.
00 = 3200 Hz
01 = 1600 Hz
10 = 800 Hz
11 = 6400 Hz
Note: The loop filter bandwidth will be twice the value
Calibration Mode Active.
This output is driven high during the DSPLL self-cal-
ibration and the subsequent initial lock acquisition
period.
Clock Validation Time for LOS.
VALTIME sets the clock validation times for recovery
from an LOS alarm condition. When VALTIME is
high, the validation time is approximately
13 seconds. When VALTIME is low, the validation
time is approximately 100 ms.
Reserved—GND.
This pin must be tied to GND for normal operation.
Reserved—No Connect.
This pin must be left unconnected for normal
operation.
Select 3.3 V V
This is an enable pin for the internal regulator. To
enable the regulator, connect this pin to the V
pins.
3.3 V Supply.
3.3 V power is applied to the V
supply bypassing/decoupling for this configuration is
indicated in the typical application diagram for 3.3 V
supply operation.
2.5 V Supply.
These pins provide a means of connecting the
compensation network for the on-chip regulator.
indicated when DBLBW is set high.
DD
Supply.
Description
DD33
pins. Typical
Si5320
DD33
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