SI4133W-BM Silicon Laboratories Inc, SI4133W-BM Datasheet - Page 18

• Manufacturer Part Number: SI4133W-BM
• Description: IC SYNTHESIZER RF DUALBAND 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4133W-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 2.6GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1115

Si4133W
Output Frequencies
The IF and RF output frequencies are set by
programming the R- and N-Divider registers. Each PLL
has its own R and N registers so that each can be
programmed independently. Programming either the R-
or N-Divider register for RF1 or RF2 automatically
selects the associated output.
The reference frequency on the XIN pin is divided by R
and this signal is the input to the PLL’s phase detector.
The other input to the phase detector is the PLL’s VCO
output frequency divided by N. The PLL works to make
these frequencies equal. That is, after an initial transient
or
The integers R are set by programming the RF1 R-
Divider register (Register 6), the RF2 R-Divider register
(Register 7) and the IF R-Divider register (Register 8).
The values of R are limited to the range of about 7
(decimal) to 8189 depending on the phase detector gain
(see Registers 6–8 on pages 25 and 26.)
The integers N are set by programming the RF1 N-
Divider register (Register 3), the RF2 N-Divider register
(Register 4), and the IF N-Divider register (Register 5).
Each N-Divider is implemented as a conventional high
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed
synchronous counter.
PLL Loop Dynamics
The transient response for each PLL is determined by
its phase detector update rate f φ (equal to f
the phase detector gain programmed for each RF1,
RF2, or IF synthesizer. (See Register 1.) Four different
settings for the phase detector gain are available for
each PLL. The highest gain is programmed by setting
the two phase detector gain bits to 00 and the lowest by
setting the bits to 11. The values of the available gains
relative to the highest gain are shown in Table 7.
18
Table 7. Gain Values (Register 1)
K
P
00
01
10
11
Bits
f
OUT
f
----------- -
OUT
N
=
=
Relative P.D. Gain
N
--- - f
R
f
-----------
⋅
REF
R
REF
1/2
1/4
1/8
1
REF
/R) and
Rev. 1.1
The gain value bits must be set manually by writing to
Register 1. In general, a higher phase detector gain will
increase the speed of the PLL transient until the point at
which stability begins to be compromised. The optimal
gain depends on N. Table 8 lists recommended settings
for different values of N. For large values of N, the
output may become unstable as indicated by “x”. In that
case, to avoid unstable operation, it is recommended to
increase the phase detector update rate (by lowering R
or increasing f
frequency.
The VCO gain and loop filter characteristics are not
programmable.
The settling time for the PLL is directly proportional to its
phase detector update period T φ (T φ = 1/f φ ). During the
first 13 update periods the Si4133W executes the self-
tuning algorithm. Thereafter the PLL controls the output
frequency. Because of the unique architecture of the
Si4133W PLLs, the time required to settle the output
frequency to 0.1 ppm error is only about 25 update
periods. Thus, the total time after power-up or a change
in
frequency is well settled—including time for self-
tuning—is around 40 update periods.
Note: The “x” indicates possible unstable operation.
16384–24575
24576–57343
57344–98303
8192–16383
1024–2047
2048–4095
4096–8191
programmed
≥98304
≤1023
N
Table 8. Optimal K
REF
K
frequency
) to achieve the same output
P1
RF1
00
00
00
01
10
11
11
11
<1:0>
x
until
K
P
P2
Settings
RF2
00
00
01
10
11
11
11
<3:2>
x
x
the
synthesized
K
PI
<5:4>
00
01
10
11
11
11
IF
x
x
x