SI4122G-BM Silicon Laboratories Inc, SI4122G-BM Datasheet - Page 15

• Manufacturer Part Number: SI4122G-BM
• Description: IC SYNTHESIZER GSM RF2/IF 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4122G-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 1.5GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 1.5GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1105

Functional Description
The Si4133G is a monolithic integrated circuit that
performs IF and dual-band RF synthesis for wireless
applications such as GSM 850, E-GSM 900, DCS 1800,
and PCS 1900. Its fast transient response also makes
the Si4133G especially well suited to GPRS and
HSCSD multislot applications where channel switching
and settling times are critical. This integrated circuit
(IC), with a minimal number of external components,
completes the frequency synthesis function.
The Si4133G has three complete phase-locked loops
(PLLs) with integrated voltage-controlled oscillators
(VCOs). The low phase noise of the VCOs makes the
Si4133G
communications applications. Phase detectors, loop
filters, and reference dividers are also integrated. The
IC is programmed with a three-wire serial interface.
One PLL is provided for IF synthesis, and two PLLs are
provided for dual-band RF synthesis. One RF VCO is
optimized to have its center frequency set between
947 and 1720 MHz, whereas the second RF VCO is
optimized to have its center frequency set between
789 and 1429 MHz. The IF VCO is optimized to have its
center frequency set between 526 and 952 MHz. Each
PLL can adjust its output frequency by ±5% relative to
its VCO center frequency.
The center frequency of each VCO is set by connection
of an external inductance. Inaccuracies in the value of
the inductance are compensated for by the Si4133G’s
proprietary self-tuning algorithm. This algorithm is
initiated each time the PLL is powered-up (by either the
PWDN pin or by software) and/or each time a new
output frequency is programmed.
The two RF PLLs share a common output pin, so only
one PLL is active at a time. Because the two VCOs can
be set to have widely separated center frequencies, the
RF output can be programmed to service different
frequency bands, thus the Si4133G is ideal for dual-
band cellular handsets.
The unique PLL architecture in the Si4133G produces a
transient response that is superior in speed to
fractional-N architectures without the high phase noise
or spurious modulation effects often associated with
those designs.
Serial Interface
A timing diagram for the serial interface is shown in
Figure 2 on page 7. Figure 3 on page 7 shows the
format of the serial word.
suitable
for
demanding
wireless
Rev. 1.4
The Si4133G is programmed serially with 22-bit words
comprised of 18-bit data fields and 4-bit address fields.
When the serial interface is enabled (i.e., when SEN is
low) data and address bits on the SDATA pin are
clocked into an internal shift register on the rising edge
of SCLK. Data in the shift register is then transferred on
the rising edge of SEN to the internal data register
identified in the address field. The serial interface is
disabled when SEN is high.
Table 10 on page 20 summarizes the data register
functions and addresses. The internal shift register
ignores leading bits before the 22 required bits.
Setting the VCO Center Frequencies
The PLLs can adjust the IF and RF output frequencies
±5% with respect to their VCO center frequencies. Each
center frequency is established by the value of an
external inductance connected to the respective VCO.
Manufacturing tolerances of ±10% for the external
inductances
compensates for inaccuracies in each inductance by
executing a self-tuning algorithm after PLL powerup or
after a change in the programmed output frequency.
Because the total tank inductance is in the low nH
range, the inductance of the package must be
considered when determining the correct external
inductance. The total inductance (L
each VCO is the sum of the external inductance (L
and the package inductance (L
nominal capacitance (C
inductance, and the center frequency is as follows:
Tables 6 and 7 summarize the characteristics of each
VCO.
f
CEN
f
are
CEN
=
------------------------------------------------------------------------
2π
=
(
acceptable.
---------------------------------------------- -
2π L
L
or
NOM
PKG
TOT
) in parallel with the total
+
1
1
L
PKG
EXT
×
C
)
NOM
). Each VCO has a
×
Si4133G
TOT
C
The
NOM
) presented to
Si4133G
EXT
15
)