SI4112-BM Silicon Laboratories Inc, SI4112-BM Datasheet - Page 17
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI4112-BM
Manufacturer Part Number
SI4112-BM
Description
IC SYNTHESIZER IF-ONLY 28MLP
Manufacturer
Silicon Laboratories Inc
Type
Frequency Synthesizerr
Datasheet
1.SI4112-BM.pdf
(36 pages)
Specifications of SI4112-BM
Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
No/No
Frequency - Max
1GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Frequency-max
1GHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
336-1097
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI4112-BM
Manufacturer:
NXP
Quantity:
2 122
As a design example, consider that the goal is to
synthesize frequencies in a 25 MHz band between
1120 and 1145 MHz using the Si4133-BT. The center
frequency should be defined as midway between the
two extremes, or 1132.5 MHz. The PLL can adjust the
VCO output frequency ±5% of the center frequency, or
±56.6 MHz of 1132.5 MHz (i.e., from approximately
1076 to 1189 MHz). The RF2 VCO has a C
4.8 pF. A 4.1 nH inductance in parallel with this
capacitance yields the required center frequency. An
external inductance of 1.8 nH should be connected
between RFLC and RFLD as shown in Figure 15. This,
Figure 15. External Inductance Connection
VCO f
VCO f
RF1
RF2
RF1
RF2
Table 7. Si4133-BM VCO Characteristics
Table 6. Si4133-BT VCO Characteristics
IF
IF
Min
526
CEN
Min
526
CEN
947 1720
789 1429
947 1720
789 1429
(MHz)
(MHz)
Range
Range
Max
Max
952
952
L
L
C
C
PKG
PKG
2
2
(pF)
(pF)
4.3
4.8
6.5
4.3
4.8
6.5
NOM
NOM
L
L
(nH)
(nH)
2.0
2.3
2.1
1.5
1.5
1.6
PKG
PKG
L
L
Min
Min
0.0
0.3
2.2
0.5
1.1
2.7
EXT
EXT
(nH)
(nH)
Range
Range
L
Max
12.0
Max
12.5
EXT
4.6
6.2
5.1
7.0
NOM
Rev. 1.4
of
in addition to 2.3 nH of package inductance, presents
the
manufacturing, the external inductance can vary ±10%
of its nominal value and the Si4133 corrects for the
variation with the self-tuning algorithm.
For more information on designing the external trace
inductors, refer to Application Note 31: Inductor Design
for the Si41xx Synthesizer Family.
Extended Frequency Operation
The Si4133 may operate at an extended frequency
range of 1850 MHz to 2050 MHz by connecting the
RFLA and RFLB pins directly. For information on
configuring
operation, refer to Application Note 41: Extended
Frequency Operation of Silicon Laboratories Frequency
Synthesizers.
Self-Tuning Algorithm
The self-tuning algorithm is initiated immediately after
powerup of a PLL or, if the PLL is already powered, after
a change in its programmed output frequency. This
algorithm attempts to tune the VCO so that its free-
running frequency is near the required output frequency.
In
manufacturing tolerance errors in the value of the
external inductance connected to the VCO. It also
reduces the frequency error for which the PLL must
correct to get the precise required output frequency. The
self-tuning algorithm leaves the VCO oscillating at a
frequency in error by somewhat less than 1% of the
desired output frequency.
After self-tuning, the PLL controls the VCO oscillation
frequency. The PLL completes frequency locking,
eliminating any remaining frequency error. From then
on, it maintains frequency-lock, compensating for
effects of temperature and supply voltage variations.
The Si4133’s self-tuning algorithm compensates for
component value errors at any temperature within the
specified temperature range. However, the ability of the
PLL to compensate for drift in component values that
occur
inductances
approximately ±150 ppm/
for changes in temperature of approximately ±30
Applications where the PLL is regularly powered down
or the frequency is periodically reprogrammed minimize
or eliminate the potential effects of temperature drift
because the VCO is re-tuned in either case. In
applications where the ambient temperature can drift
substantially after self-tuning, it might be necessary to
monitor the lock-detect bar (LDETB) signal on the
AUXOUT pin to determine whether a PLL is about to
doing
correct
after
so,
the
self-tuning
total
with
the
Si4133
inductance
algorithm
o
C, the PLL can maintain lock
temperature
is
for
limited.
extended
to
compensates
the
Si4133
For
coefficients
VCO.
frequency
external
o
C.
for
17
In