MC88915TFN160 Freescale Semiconductor, MC88915TFN160 Datasheet - Page 12

• Manufacturer Part Number: MC88915TFN160
• Description: IC DRIVER CLK PLL 160MHZ 28-PLCC
• Manufacturer: Freescale Semiconductor
• Type: Clock Driver, Fanout Distribution, Multiplexerr

Specifications of MC88915TFN160

• Pll: Yes
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 3:8
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 160MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General AC Specification Notes
1. Several specifications can only be measured when the
4. A 1M resistor tied to either Analog V
12
MC88915TFN55, 70 and 100 are in phase–locked
operation. It is not possible to have the part in phase–lock
on
characterization techniques were used to guarantee those
specifications which cannot be measured on the ATE.
MC88915TFN55, 70 and 100 units were fabricated with
key transistor properties intentionally varied to create a 14
cell designed experimental matrix. IC performance was
characterized over a range of transistor properties
(represented by the 14 cells) in excess of the expected
process variation of the wafer fabrication area, to set
performance limits of ATE testable specifications within
those which are to be guaranteed by statistical
characterization. In this way all units passing the ATE test
will meet or exceed the non–tested specifications limits.
shown in Figure 2 is required to ensure no jitter is present
on the MC88915T outputs. This technique causes a phase
offset between the SYNC input and the output connected
to the FEEDBACK input, measured at the input pins. The
t
temperature, and voltage. The specs were arrived at by
PD
FREQ_SEL
Level
spec describes how this offset varies with process,
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
ATE
(automated
Table 1. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations.
Any “Q” (Q0–Q4) 10 to (2X_Q FMAX Spec)/2
Any “Q” (Q0–Q4) 5 to (2X_Q FMAX Spec)/4
Feedback
Output
2X_Q
2X_Q
Q/2
Q/2
Q5
Q5
test
Applications Information for All Versions
Figure 1. MC68040 P–Clock Input Termination Scheme
equipment).
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
2.5 to (2X_Q FMAX Spec)/8
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
CC
Frequency Range (MHZ)
Allowable SYNC Input
or Analog GND as
Statistical
2. These two specs (t
3. The wiring Diagrams and explanations in Figure 5
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAXSpec)
20 to (2X_Q FMAXSpec)
output) guarantee that the MC88915T meets the 40MHz
and 33MHz MC68040 P–Clock input specification (at
80MHz and 66MHz, respectively). For these two specs to
be guaranteed by Motorola, the termination scheme
shown below in Figure 1 must be used.
demonstrate the input and output frequency relationships
for three possible feedback configurations. The allowable
SYNC input range for each case is also indicated. There
are two allowable SYNC frequency ranges, depending
whether FREQ_SEL is high or low. Although not shown, it
is possible to feed back the Q5 output, thus creating a 180
phase shift between the SYNC input and the “Q” outputs.
Table 1 below summarizes the allowable SYNC frequency
range for each possible configuration.
measuring the phase relationship for the 14 lots described
in note 1 while the part was in phase–locked operation.
The actual measurements were made with a 10MHz
SYNC input (1.0ns edge rate from 0.8V – 2.0V) with the
Q/2 output fed back. The phase measurements were
made at 1.5V. The Q/2 output was terminated at the
FEEDBACK input with 100 to V
Corresponding VCO
Frequency Range
R
p
R
p
RlSE/FALL
= 1.5 Z
to Rising SYNC Edge
Phase Relationships
o
of the “Q” Outputs
and t
CC
and 100 to ground.
PULSE
180
180
0
0
0
0
0
0
MOTOROLA
Width 2X_Q