MC145152DW2R2 Freescale Semiconductor, MC145152DW2R2 Datasheet - Page 20

• Manufacturer Part Number: MC145152DW2R2
• Description: IC PAR-IN PLL FREQ SYNTH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Type: PLL Clock/Frequency Synthesizerr

Specifications of MC145152DW2R2

• Pll: Yes
• Input: Clock
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 25MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 9 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC145152DW2TR

Design Considerations
For V
32 pF for frequencies to approximately 8.0 MHz, 20 pF for frequencies in the area of 8.0 to 15 MHz, and
10 pF for higher frequencies. These are guidelines that provide a reasonable compromise between IC
capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
C
where
C1 and C2 = external capacitors (see
The oscillator can be “trimmed” on-frequency by making a portion or all of C1 variable. The crystal and
associated components must be located as close as possible to the OSC
distortion, stray capacitance, stray inductance, and startup stabilization time. In some cases, stray
capacitance should be added to the value for C
Power is dissipated in the effective series resistance of the crystal, R
specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damage
or excessive shift in frequency. R1 in
in some cases (i.e., R1 = 0 Ω).
20
L
values. The shunt load capacitance, C
DD
C
C
C
C
in
out
a
O
= 5.0 V, the crystal should be specified for a loading capacitance, C
= 5 pF (see
= 6 pF (see
= 1 pF (see
= the crystal's holder capacitance (see
Figure
Figure
Figure
Figure 14. Parasitic Capacitances of the Amplifier
1
MC145151-2 and MC145152-2 Technical Data, Rev. 5
14)
14)
14)
Figure 15. Equivalent Crystal Networks
C
NOTE: Values are supplied by crystal manufacturer
L
=
Figure
Figure 13
C
in
(parallel resonant crystal).
C
2
C
in
L
in
, presented across the crystal can be estimated to be:
+ C
C
13)
out
out
in
limits the drive level. The use of R1 may not be necessary
1
+ C
1
and C
C
a
a
Figure
+ C
R
R
out
e
S
o
+
.
15)
X
C1 + C2
C1
C
e
L
S
O
C
•
out
C2
2
C
S
e
, in
in
Figure
and OSC
2
L
, which does not exceed
15. The drive level
out
Freescale Semiconductor
pins to minimize