MPC974FA Freescale Semiconductor, MPC974FA Datasheet - Page 6

• Manufacturer Part Number: MPC974FA
• Description: IC PLL CLOCK DRIVER 52-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Driver, Fanout Distribution, Multiplexerr

Specifications of MPC974FA

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:14
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC974
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of approximately 10
the drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
level of DC current and thus only a single terminated line can
be driven by each output of the MPC974 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 5 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC974 clock
driver is effectively doubled due to its capability to drive
multiple lines.
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC974 output buffers is
more than sufficient to drive 50
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC974. The output waveform
in Figure 6 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43 series resistor plus the output
impedance does not match the parallel combination of the
MOTOROLA
IN
IN
The MPC974 clock driver was designed to drive high
In most high performance clock networks point–to–point
The waveform plots of Figure 6 show the simulation
Figure 5. Single versus Dual Transmission Lines
resistance to V CC /2. This technique draws a fairly high
OUTPUT
OUTPUT
BUFFER
BUFFER
MPC974
MPC974
7
7
R S = 43
R S = 43
R S = 43
transmission lines on the
Z O = 50
Z O = 50
Z O = 50
OutA
OutB0
OutB1
6
line impedances. The voltage wave launched down the two
lines will equal:
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 7 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
At the load end the voltage will double, due to the near
Since this step is well above the threshold region it will not
SPICE level output buffer models are available for
3.0
2.5
2.0
1.5
1.0
0.5
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
0
Figure 7. Optimized Dual Line Termination
Figure 6. Single versus Dual Waveforms
OUTPUT
MPC974
BUFFER
t D = 3.8956
7
2
In
OutA
7 + 36
4
R S = 36
R S = 36
25 = 25
k
6
36 = 50
TIME (nS)
t D = 3.9386
OutB
8
Z O = 50
Z O = 50
k
TIMING SOLUTIONS
10
50
12
14