LMX2335LM National Semiconductor, LMX2335LM Datasheet - Page 19

• Manufacturer Part Number: LMX2335LM
• Description: IC FREQ SYNTHESIZER DUAL 16-SOIC
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2335LM

• Pll: Yes with Bypass
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: No/No
• Frequency - Max: 1.1GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 1.1GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LMX2335LM

Application Information
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop band-
width, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison
frequency also diminishes, the spurs would have increased
by approximately 6 dB. In the proposed Fastlock scheme,
the higher spur levels and wider loop filter conditions would
exist only during the initial lock-on phase — just long enough
to reap the benefits of locking faster. The objective would be
to open up the loop bandwidth but not introduce any addi-
tional complications or compromises related to our original
design criteria. We would ideally like to momentarily shift the
curve Figure 4 over to a different cutoff frequency, illustrated
by dotted line, without affecting the relative open loop gain
and phase relationships. To maintain the same gain/phase
relationship at twice the original cutoff frequency, other terms
in the gain and phase equations 4 and 5 will have to com-
pensate by the corresponding “1/w” or “1/w
nation of equations 3 and 5 indicates the damping resistor
variable R2 could be chosen to compensate with “w” terms
for the phase margin. This implies that another resistor of
equal value to R2 will need to be switched in parallel with R2
during the initial lock period. We must also insure that the
magnitude of the open loop gain, H(s)G(s) is equal to zero at
wp’ = 2 wp. K
VCO
, Kφ, N, or the net product of these terms
FIGURE 4. Open Loop Response Bode Plot
(Continued)
2
FIGURE 5. Fastlock PLL Architecture
” factor. Exami-
19
can be changed by a factor of 4, to counteract with w
present in the denominator of equation 3. The Kφ term was
chosen to complete the transformation because it can
readily be switched between 1X and 4X values. This is
accomplished by increasing the charge pump output current
from 1 mA in the standard mode to 4 mA in Fastlock.
Fastlock Circuit Implementation
A diagram of the Fastlock scheme as implemented in Na-
tional Semiconductors LMX2335L/36L PLL is shown in Fig-
ure 5. When a new frequency is loaded, and the RF1 I
is set high, the charge pump circuit receives an input to
deliver 4 times the normal current per unit phase error while
an open drain NMOS on chip device switches in a second
R2 resistor element to ground. The user calculates the loop
filter component values for the normal steady state consid-
erations. The device configuration ensures that as long as a
second identical damping resistor is wired in appropriately,
the loop will lock faster without any additional stability con-
siderations to account for. Once locked on the correct fre-
quency, the user can return the PLL to standard low noise
operation by sending a MICROWIRE instruction with the
RF1 I
charge on the loop filter capacitors and is enacted synchro-
nous with the charge pump output. This creates a nearly
seamless change between Fastlock and standard mode.
CPo
bit set low. This transition does not affect the
01280716
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01280717
CPo
2
term
bit