CY2213ZXC-2T Cypress Semiconductor Corp, CY2213ZXC-2T Datasheet - Page 3

• Manufacturer Part Number: CY2213ZXC-2T
• Description: IC PROG PECL CLOCK GEN 16-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY2213ZXC-2T

• Number Of Circuits: 1
• Package / Case: 16-TSSOP
• Pll: Yes
• Input: Crystal
• Output: LVPECL
• Ratio - Input:output: 1:2
• Differential - Input:output: No/Yes
• Frequency - Max: 400MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 500MHz
• Maximum Input Frequency: 133 MHz
• Minimum Input Frequency: 1 MHz
• Output Frequency Range: 125 MHz to 500 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07263 Rev. *E
Serial Interface Address for the CY2213
Serial Interface Programming for the CY2213
To program the CY2213 using the two-wire serial interface, set
the SELPQ bit HIGH. The default setting of this bit is LOW. The
P and Q values are determined by the following formulas:
P
Q
Data0
Data1
Data2
final
final
A6
1
= (P
= Q
1 bit
S
Data 1
5..0
7..0
8 bits
S
S
S
S
Slave Address
QCNTBYP
d a ta
clk
+ 2.
Reserved
data
+ 3) * 2
clk
P<7>
b7
7 bits
S
A5
clk
1
S
_ in
1 bit
Ack
clk
_ C
Start (S)
Reserved
SELPQ
P<6>
M a s te r D e vic e
P
b6
R/W
1 bit
A4
0
1 bit
Ack
S
Figure 2. Serial Interface Specifications
S
d a ta
Reserved
d ata
Fig. 2 Serial Interface Specifications
Figure 3. CY2213 Transfer Format
_ C
Q<5>
P<5>
_ in
Figure 1. Device Connections
b5
valid data
Dummy Byte 0
8 bits
A3
0
R
p
Reserved
Q<4>
P<4>
b4
If the QCNTBYP bit is set HIGH, then Q
of 1. The default setting of this bit is LOW.
If the SELPQ bit is set LOW, the PLL multipliers will be set
using the values in the Select Function Table.
CyberClocks™ has been developed to generate P and Q
values for stable PLL operation. This software is downloadable
from www.cypress.com.
Acknowledge
S
1 bit
Ack
c lk
_ in
A2
1
R
Reserved
p
Dummy Byte 1
Q<3>
P<3>
b3
S lav e D ev ice
8 bits
V
D D
A1
0
Reserved
S
S
d ata
Q<2>
P<2>
d ata
1 bit
Ack
b2
_ C
_ in
Stop (P)
Data 0
8 bits
Reserved
A0
1
Q<1>
P<1>
b1
final
defaults to a value
1 bit
Ack
CY2213
Page 3 of 10
Reserved
R/W
Q<0>
P<0>
0
b0
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