SY89536LHC Micrel Inc, SY89536LHC Datasheet - Page 6

• Manufacturer Part Number: SY89536LHC
• Description: IC SYNTHESIZR LVPECL/HSTL 64TQFP
• Manufacturer: Micrel Inc
• Series: Precision Edge®r
• Type: Clock/Frequency Synthesizerr

Specifications of SY89536LHC

• Pll: Yes with Bypass
• Input: CMOS, HSTL, LVDS, LVPECL, LVTTL, SSTL
• Output: HSTL, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:13
• Differential - Input:output: Yes/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 1.6 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Micrel, Inc.
V
Symbol
f
f
t
t
t
t
t
t
t
t
t
t
t
FSEL-to-Valid Output Transition Time
t
Note 8.
Note 9.
Note 10. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
Note 11. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T
Note 12. Period Jitter definition: For a specified amount of time (i.e., 1ms), there are N periods of a signal, and T
Note 13. Using recommended loop filter components.
Note 14. See “Timing Diagrams."
M9999-010808
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IN
OUT
VCO
skew
LOCK
JITTER
pw
DC
r
OUTPUT_RESET
HOLD_FSEL
SETUP_FSEL
OUTPUT_SYNC
SETUP_OUT_SYNC
, t
CC_LOGIC
AC ELECTRICAL CHARACTERISTICS
f
(min)
All HSTL outputs loaded with 50 to GND.
The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the
same voltage and temperature.
voltage and temperature.
T
that signal. Period jitter is defined as the variation in the period of the output signal for corresponding edges relative to T
n+1
= V
where T is the time between rising edges of the output signal.
CC
Parameter
Reference Input Frequency
Output Frequency Range
Internal VCO Frequency Range
Within Device Skew
Part-to-Part Skew
Maximum PLL Lock Time
Cycle-to-Cycle Jitter
Period Jitter
Minimum Pulse Width
Target PLL Loop Bandwidth
f
Output Rise/Fall Time
(20% to 80%)
OUT
A/C = +3.3V 10%, V
Duty Cycle
Feedback Divider Ratio: 66
Feedback Divider Ratio: 30
Within Bank PECL
Within Bank HSTL
Bank-to-Bank
LVPECL_Out
CCO
HSTL_Out
(Pk-to-Pk)
B = +1.8V 10%
(rms)
Condition
Note 9
Note 9
Note 9
Note 10
Note 11
Note 12
Note 13
Note 13
Note 14
Note 14
Note 14
Note 14
6
n
is defined as the average period of
33.33
Min
600
100
500
14
50
45
—
—
—
—
—
—
—
—
—
—
—
—
5
5
1
Typ
250
1.0
2.0
60
50
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
n
.
Precision Edge
1000
Max
160
500
150
200
400
400
JITTER_CC
50
75
10
50
50
55
10
—
—
—
—
—
—
—
—
SY89536L
clock cycle
Units
VCO
MHz
MHz
MHz
MHz
MHz
ms
=T
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ps
%
n
–
®