SY89533LHC Micrel Inc, SY89533LHC Datasheet - Page 6

• Manufacturer Part Number: SY89533LHC
• Description: IC SYNTHESIZR LVPECL/LVDS 64TQFP
• Manufacturer: Micrel Inc
• Series: Precision Edge®r
• Type: Clock/Frequency Synthesizerr

Specifications of SY89533LHC

• Pll: Yes
• Input: Crystal
• Output: LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:13
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Micrel, Inc.
V
Notes:
1. Fundamental mode crystal.
2. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same
3. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
4. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T
5. Loop filter values shown in Figure 3.
6. Using recommended loop filter components. See “Functional Description, External Loop Filter Considerations.”
M9999-010808
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Symbol
f
f
t
t
t
t
t
t
t
t
t
t
t
FSEL-to-Valid Output Transition Time
t
CC_LOGIC
IN
OUT
VCO
skew
LOCK
JITTER
pw
DC
r
OUTPUT_RESET
HOLD_FSEL
SETUP_FSEL
OUTPUT_SYNC
SETUP_OUT_SYNC
, t
AC ELECTRICAL CHARACTERISTICS
voltage and temperature.
voltage and temperature.
where T is the time between rising edges of the output signal.
f
(min)
= V
Xtal Input Frequency Range
Output Frequency Range
VCO Frequency Range
External VCO Frequency
Within Device
Pin-to-Pin Skew, Bank-to-Bank
Part-to-Part Skew
Maximum PLL Lock Time
Cycle-to-Cyle Jitter
Total Jitter
Minimum Pulse Width
Target PLL Loop Bandwidth
External VCO Clock Input
f
Output Rise/Fall Time
(20% to 80%)
OUT
Feedback Divider Ratio: 72
Feedback Divider Ratio: 34
CCA
(See Timing Diagrams)
Duty Cycle
(Within Same Logic Type)
= V
(SY89533L) LVDS_Out
(Between Logic Types)
Parameter
(5)
CCO
(2)
A/B/C = +3.3V 10%
(3)
(4)
External VCO
LVPECL_Out
Internal VCO
(pk-to-pk)
(1)
(rms)
(6)
(6)
Min.
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T
A
Typ.
= 0 C
1.0
2.0
60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
Max.
1000
1250
1.25
6
150
400
450
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
33.33
Min.
600
500
14
50
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
5
1
T
A
= +25 C
Typ.
250
300
1.0
2.0
60
25
20
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
622.08
Max.
1000
1250
1.25
500
200
400
450
150
18
50
50
10
50
50
—
—
—
55
10
—
—
—
—
1
Min.
600
50
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T
A
= +85 C
Typ.
1.0
2.0
60
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
JITTER_CC
Precision Edge
Max.
1000
1250
1.25
SY89532/33L
150
200
400
450
50
50
10
50
55
—
—
—
—
—
—
—
—
—
—
—
—
—
=T
n
–T
clock cycle
VCO
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
GHz
n+1
ms
ps
ps
ps
ps
ps
ps
ns
ps
ns
ns
ns
ps
%
s
®