ADF4212BRU-REEL7 Analog Devices Inc, ADF4212BRU-REEL7 Datasheet - Page 10

• Manufacturer Part Number: ADF4212BRU-REEL7
• Description: IC PLL FREQ SYNTHESIZER 20-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF/IF)r

Specifications of ADF4212BRU-REEL7

• Rohs Status: RoHS non-compliant
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 2.7GHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 2.7GHz

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic.
The PFD includes a fixed-delay element that sets the width of
the antibacklash pulse. This is typically 3 ns. This pulse ensures
that there is no deadzone in the PFD transfer function and gives
a consistent reference spur level.
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF421x family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by P3, P4, P11, and P12. See Tables
III and V. Figure 6 shows the MUXOUT section in block dia-
gram form.
ADF4210/ADF4211/ADF4212/ADF4213
IF/RF ANALOG LOCK DETECT
RF ANALOG LOCK DETECT
CP OUTPUT
IF ANALOG LOCK DETECT
R DIVIDER
N DIVIDER
R DIVIDER
N DIVIDER
RF R COUNTER OUTPUT
RF N COUNTER OUTPUT
IF R COUNTER OUTPUT
IF N COUNTER OUTPUT
DIGITAL LOCK DETECT
HI
HI
D1
D2
CLR1
CLR2
U1
U2
Q1
Q2
UP
DOWN
DELAY
MUX
CONTROL
U3
DV
DGND
CPGND
DD
V
P
MUXOUT
CHARGE
PUMP
CP
Lock Detect
MUXOUT can be programmed for two types of lock detect:
Digital Lock Detect and Analog Lock Detect. Digital Lock
Detect is active high. It is set high when the phase error on three
consecutive Phase Detector cycles is less than 15 ns. It will stay
set high until a phase error of greater than 25 ns is detected on
any subsequent PD cycle. The N-channel open-drain analog
lock detect should be operated with an external pull-up resistor
of 10 kΩ nominal. When lock has been detected, it is high with
narrow low-going pulses.
RF/IF INPUT SHIFT REGISTER
The ADF421x family digital section includes a 24-bit input shift
register, a 14-bit IF R counter and a 18-bit IF N counter, com-
prising a 6-bit IF A counter and a 12-bit IF B counter. Also
present is a 14-bit RF R counter and an 18-bit RF N counter,
comprising a 6-bit RF A counter and a 12-bit RF B counter.
Data is clocked into the 24-bit shift register on each rising edge
of CLK. The data is clocked in MSB first. Data is transferred
from the shift register to one of four latches on the rising edge of
LE. The destination latch is determined by the state of the two
control bits (C2, C1) in the shift register. These are the two LSBs
DB1, DB0 as shown in the timing diagram of Figure 1. The
truth table for these bits is shown in Table VI. Table I shows a
summary of how the latches are programmed.
Control Bits
C2
0
0
1
1
C1
0
1
0
1
Table I. C2, C1 Truth Table
Data Latch
IF R Counter
IF AB Counter (A and B)
RF R Counter
RF AB Counter (A and B)