ADF4206BRU-REEL7 Analog Devices Inc, ADF4206BRU-REEL7 Datasheet - Page 7

• Manufacturer Part Number: ADF4206BRU-REEL7
• Description: IC PLL FREQ SYNTHESIZER 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4206BRU-REEL7

• Rohs Status: RoHS non-compliant
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 550MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 550MHz

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
ADF4206
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
N/A
N/A
N/A
N/A
ADF4208
Pin No.
1
2
3
4
5
8
9
10
11
12
13
16
17
18
19
20
6
7
14
15
DGND
Figure 3. 16-Lead TSSOP Pin Configuration
MUXOUT
OSC
CP
OSC
RF1
V
DD
V
OUT
RF1
RF1
P
IN
IN
1
1
1
2
3
4
5
6
7
8
Mnemonic
V
V
CP
DGND
RF1
OSC
OSC
MUXOUT
CLK
DATA
LE
RF2
DGND
CP
V
V
RF1
AGND
AGND
RF2
DD
P
P
DD
(Not to Scale)
1
2
RF1
RF2
1
2
ADF4206
TOP VIEW
IN
IN
IN
IN
IN
OUT
/RF1
/RF2
B
B
RF1
RF2
RF1
RF2
IN
IN
A
A
15
14
13
12
11
10
16
9
V
V
CP
DGND
RF2
LE
DATA
CLK
DD
P
Description
Positive Power Supply for the RF1 Section. A 0.1 μF capacitor is connected between this pin
and DGND
must have the same potential as V
Power Supply for the RF1 Charge Pump. This is greater than or equal to V
Output from the RF1 Charge Pump. This is normally connected to a loop filter that drives the
input to an external VCO.
Ground Pin for the RF1 Digital Circuitry.
Input to the RF1 Prescaler. This low level input signal is taken from the RF1 VCO.
Oscillator Input. It has a V
Oscillator Output.
This multiplexer output allows the IF/RF lock detect, the scaled RF, or the scaled reference
frequency external access. See Figure 30.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 22-bit shift register on the CLK rising edge. This input is a high impedance
CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded
into one of the four latches, the latch being selected using the control bits.
Input to the RF2 Prescaler. This low level input signal is normally ac-coupled to the external
VCO.
Ground Pin for the RF2, Digital, Interface, and Control Circuitry.
Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives the
input to an external VCO.
Power Supply for the RF2 Charge Pump. This is greater than or equal to V
Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1 μF capacitor is
connected between this pin and DGND
and 5.5 V. V
Complementary Input to the RF1 Prescaler of the ADF4208. This point is decoupled to the
ground plane with a small bypass capacitor.
Ground Pin for the RF1 Analog Circuitry.
Ground Pin for the RF2 Analog Circuitry.
Complementary Input to the RF2 Prescaler. This point is decoupled to the ground plane with a
small bypass capacitor.
2
RF2
2
IN
RF2
RF1
DD
2 must have the same potential as V
(the RF1 ground pin). V
Rev. A | Page 7 of 24
DD
/2 threshold and is driven from an external CMOS or TTL logic gate.
DD
2.
DD
1 should have a value of between 2.7 V and 5.5 V. V
RF2
(the RF2 ground pin). V
DGND
AGND
Figure 4. 20-Lead TSSOP Pin Configuration
MUXOUT
OSC
RF1
RF1
OSC
CP
V
V
IN
IN
OUT
DD
RF1
RF1
RF1
P
IN
A
B
1
1
DD
10
1.
1
2
3
4
5
6
7
8
9
(Not to Scale)
ADF4208
TOP VIEW
ADF4206/ADF4208
DD
20
19
18
17
16
15
14
13
12
11
2 has a value between 2.7 V
AGND
V
CP
DGND
RF2
RF2
LE
DATA
CLK
V
DD
P
2
DD
DD
RF2
2
IN
IN
.
.
RF2
RF2
A
B
DD
1