NB7N017MMNG ON Semiconductor, NB7N017MMNG Datasheet - Page 3

• Manufacturer Part Number: NB7N017MMNG
• Description: IC DIVIDER 8BIT DUAL CML 52-QFN
• Manufacturer: ON Semiconductor
• Type: Clock Dividerr

Specifications of NB7N017MMNG

• Pll: No
• Input: CML, ECL, LVCMOS, LVDS, LVTTL
• Output: CML
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 3.5GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: ±3 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-VFQFN Exposed Pad
• Frequency-max: 3.5GHz
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Table 1. PIN DESCRIPTION
1. All high speed inputs and outputs are differential to improve performance.
2. All single−ended inputs are CMOS and NECL/ECL compatible.
3. All V
4. The NC pins are electrically connected to the die and must be left open.
5. CML outputs require 50 W receiver termination resistor to V
6. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied
CLK
CE
MR
SEL
PLa, PLb
TC
Pa[0:7], Pb[0:7]
V
V
VTCLK, VTCLK,
VTSEL, VTSEL
VTCE, VTCE
V
NC
EP
CC
EE
BB
exposed pad (EP) on package bottom (see case drawing) must be attached to a heat−sinking conduit. Exposed pad is bonded to the lowest
voltage potential, V
then the device will be susceptible to self−oscillation.
Pin Name
CC
and V
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EE
pins must be externally connected to external power supply voltage to guarantee proper device operation. The thermally
ECL, CML, LVCMOS,
ECL, CML, LVCMOS,
ECL, CML, LVCMOS,
LVDS, LVTTL Input
LVDS, LVTTL Input
LVDS, LVTTL Input
EE
CMOS, ECL Input
CMOS, ECL Input
CMOS, ECL Input
.
CML Output
Termination
Output
Power
Power
N/A
I/O
−
Default
State
High
Low
Low
−
−
−
−
−
−
−
−
−
−
Single/Differential
http://onsemi.com
(Notes 1 and 2)
Differential
Differential
Differential
Differential
Differential
NB7N017M
CC
Single
Single
Single
for proper operation.
−
−
−
−
−
3
Clock
Clock Enable
Asynchronous Master Reset: Counter set to 0000 0000 to
reload at next CLK pulse, REGa and REGb = 1111 1111 and
TC = 1.
Divide Select
Parallel Load Counter Latch from Pa[0:7], Pb[0:7] (Level
Triggered)
Terminal Count, 16 mA CML output with 50 W Source
Termination to V
Counter Program Pins. CMOS and PECL/NECL compatible
Pa7 = MSB, Pb7 = MSB
Positive Supply
Negative Supply
50 W Internal Input Termination Resistor (Note 6)
CMOS/ECL Reference Voltage Output
No Connect (Note 4)
Exposed Pad (Note 3)
CC
(Note 5)
Description