FS7145-02G-XTP ON Semiconductor, FS7145-02G-XTP Datasheet
FS7145-02G-XTP
Specifications of FS7145-02G-XTP
Related parts for FS7145-02G-XTP
FS7145-02G-XTP Summary of contents
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... Very low “cumulative” jitter 2.0 Description The FS714x (FS7140x or FS7145x monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of electronic systems. Via the I The length of the reference and feedback dividers, their fine granularity and the flexibility of the post divider make the FS714x the most flexible stand-alone PLL clock generator available ...
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FS714x Table 1: FS7140 Pin Descriptions Pin Type Name Description 1 DI SCL Serial interface clock (requires an external pull-up) 2 DIO SDA Serial interface data input/output (requires an external pull-up ADDR0 Address select bit “0” ...
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... FS714x Table 2: FS7145 Pin Descriptions Pin Type Name Description 1 DI SCL Serial interface clock (requires an external pull-up) 2 DIO SDA Serial interface data input/output (requires an external pull-up ADDR0 Address select bit “0” VSS Ground 5 AI XIN Crystal oscillator feedback 6 AO XOUT ...
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FS714x 4.1.1. Reference Divider The reference divider is designed for low phase jitter. The divider accepts the output of either the crystal oscillator circuit or an external reference frequency. The reference divider bit divider, and can be ...
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FS714x When not using the REF input preferred to leave it floating or connected to V 4.1.6. Feedback Divider Source MUX The source of frequency for the feedback divider may be selected to be either the output of ...
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... Kohms 4.3 SYNC Circuitry The FS7145 supports nearly instantaneous adjustment of the output CLK phase by the SYNC input. Either edge direction of SYNC (positive-going or negative-going) is supported. Example (positive-going SYNC selected): Upon the negative edge of SYNC input, a sequence begins to stop the CLK output. Upon the positive edge, CLK resumes operation, synchronized to the phase of the SYNC input (plus a deterministic delay). This is performed by control of the device post-divider. Phase resolution equal to ½ ...
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FS714x 5.1.3. STOP Data Transfer A low to high transition of the SDA line while SCL input is high indicates a STOP condition. All commands to the device must be followed by a STOP condition. 5.1.4. Data Valid The state ...
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FS714x 5.2.3. Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low the register ...
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FS714x Figure 4: Random Register Write Procedure Figure 5: Random Register Read Procedure Figure 6: Sequential Register Write Procedure Rev Page www.onsemi.com ...
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FS714x Figure 7: Sequential Register Read Procedure Rev Page www.onsemi.com ...
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FS714x 6.0 Programming Information All register bits are cleared to zero on power-up. All register bits may be read back as written. Table 3: FS7140 Register Map Address BIT 7 BIT 6 Reserved Reserved Byte 7 (Bit 63) (Bit 62) ...
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... FS714x Table 4: FS7145 Register Map Address BIT 7 BIT 6 Reserved Reserved Byte 7 (Bit 63) (Bit 62) Must be set to “0” Must be set to “0” Reserved Reserved (Bit 55) (Bit 54) Byte 6 Must be set to “0” Must be set to “0” Reserved LC (Bit 47) (Bit 46) Byte 5 Must be set to “0” ...
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... FS714x Table 8: SYNC Control Bits (FS7145 only) Name Description SYNCEN Sync enable [0] = disabled / [1] = enabled SYNCPOL Sync polarity [0] = negative edge / [1] = positive edge Table 9: Post Divider Control Bits Name Description Post divider # modulus P1 [0000] [0001] [0010] [0011] [0100] [0101] [0110] POST1[3:0] [0111] [1000] ...
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FS714x 7.0 Electrical Specifications Table 10: Absolute Maximum Ratings Parameter Supply voltage ground) SS Input voltage, dc Output voltage, dc Input clamp current < > Output clamp current, ...
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FS714x Table 12: DC Electrical Specifications Parameter Overall Supply current, dynamic Supply current, static Serial Communication I/O (SDA, SCL) High-level input voltage Low-level input voltage Hysteresis voltage Input leakage current Low-level output sink current (SDA) Address Select Input (ADDR0, ADDR1) ...
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FS714x Table 13: AC Timing Specifications Parameter Symbol Overall Output frequency* f o(max) VCO frequency* f VCO CMOS mode rise time CMOS mode fall time PECL mode rise time PECL mode fall time* t ...
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FS714x Figure 8: Bus Timing Data Figure 9: Data Transfer Sequence Rev Page www.onsemi.com ...
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FS714x 8.0 Package Information for ‘Green’ and ‘Non-Green’ Table 15: 16-pin SOIC (0.150") Package Dimensions Dimensions Inches Millimeters Min. Max. Min. Max. A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1.40 1.55 B 0.013 0.019 ...
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... FS714x 9.0 Ordering Information Part Number Package FS7145-01-XTD 16-pin (0.150”) SOIC FS7145-01-XTP 16-pin (0.150”) SOIC FS7140-02G-XTD 16-pin (5.3mm) SSOP ‘Green’ or lead-free packaging 16-pin (5.3mm) SSOP FS7140-02G-XTP ‘Green’ or lead-free packaging FS7140-01G-XTD 16-pin (0.150”) SOIC ‘Green’ or lead-free packaging FS7140-01G-XTP 16-pin (0.150” ...