DS1089LU-A29+T Maxim Integrated Products, DS1089LU-A29+T Datasheet - Page 9

IC ECONOSCILL 3.3V SS 8-USOP

DS1089LU-A29+T

Manufacturer Part Number
DS1089LU-A29+T
Description
IC ECONOSCILL 3.3V SS 8-USOP
Manufacturer
Maxim Integrated Products
Series
EconOscillator™r
Type
Clock Generatorr
Datasheet

Specifications of DS1089LU-A29+T

Pll
No
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
No/No
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency-max
-
When dither is enabled (by selecting a dither frequency
setting greater than 0 with SPRD high), the master
oscillator frequency is dithered around the center fre-
quency by the selected percentage from the pro-
grammed f
is programmed to 40MHz (factory setting) and the
dither amount is programmed to ±1%, the frequency of
f
modulation frequency determined by the selected
dither frequency. Continuing with the same example, if
J1 = 0 and J0 = 1, selecting f
dither frequency would be 19.531kHz.
The DS1089L registers are used to change the dither
amount, output frequency, and slave address. A bit
summary of the registers is shown in Table 4. Once pro-
grammed into EEPROM, the settings only need to be
reprogrammed if it is desired to reconfigure the device.
Bits 7 to 6:
Bit 5:
Bit 4:
Bits 3 to 0:
Table 4. Register Summary
X = “don’t care”
x = values depend on custom settings
MOSC
PRESCALER
ADDR
WRITE EE
REGISTER
3.3V Center Spread-Spectrum EconOscillator™
will dither between 39.6MHz and 40.4MHz at a
MOSC
Dither Frequency. The J1 and J0 bits
control the dither frequency applied to the
output. See Table 2 for divider settings. If
either of bits J1 or J0 is high and SPRD is
high, dither is enabled.
Output Low or Hi-Z. The LO/HIZ bit
determines the state of the output during
power-down. While the output is deacti-
vated, if the LO/HIZ bit is set to 0, the out-
put will be high impedance (high-Z). If the
LO/HIZ bit is set to 1, the output will be
driven low.
Reserved.
Prescaler Divider. The prescaler bits (bits
P3 to P0) divide the master oscillator fre-
quency by 2
Any prescaler bit value entered that is
greater than 8 will decode as 8. See Table
1 for prescaler settings.
ADDR
(see Figure 2). For example, if f
0Dh
02h
3Fh
Register Summary
x
BIT7
where x can be from 0 to 8.
PRESCALER Register
J1
J3
MOSC
J0
J2
_____________________________________________________________________
/ 2048, then the
LO/
HIZ
OE
X
X
MOSC
BINARY
No Data
WC
P3
Bits 7 to 6:
Bit 5:
Bit 4:
Bit 3:
Bits 2 to 0:
Figure 2. Output Frequency vs. Dither Rate
OR 8% OF f
OR 8% OF f
PROGRAMMED
P2
A2
(+1, 2, 4,
(-1, 2, 4,
MOSC
MOSC
f
MOSC
P1
A1
)
)
Dither Percentage. The J3 and J2 bits
control the selected dither amplitude (%).
When both J3 and J2 are set to 0, the
default dither rate is ±1%.
Output Enable. The OE bit and the OE
pin state determine if the output is on
when the device is active (PDN = V
(OE = 0 OR OE is high) AND the PDN pin
is high, the output will be driven.
Reserved.
Write Control. The WC bit determines if
the EEPROM is to be written after register
contents have been changed. If WC = 0
(default), EEPROM is written automatically
after a write. If WC = 1, the EEPROM is
only written when the WRITE EE command
is issued. See the WRITE EE Command
section for more information.
Address. The A0, A1, A2 bits determine
the lower nibble of the I
BIT0
P0
A0
f
MOD
1
xx100000b
DEFAULT
xx00xxxxb
TIME
IF DITHER AMOUNT = 0%
ADDR Register
2
C slave address.
ACCESS
R/W
R/W
DITHER
AMOUNT
(2, 4, 8,
OR 16%)
IH
). If
9

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