NB2308AI2DR2G ON Semiconductor, NB2308AI2DR2G Datasheet
NB2308AI2DR2G
Specifications of NB2308AI2DR2G
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NB2308AI2DR2G Summary of contents
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NB2308A 3.3 V Zero Delay Clock Buffer The NB2308A is a versatile, 3.3 V zero delay buffer designed to distribute high- -speed clocks available pin package. The part has an on- -chip PLL which locks ...
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REF ÷2 Extra Divider (--5H (see Figures 11, 12, 13, 14 and 15 for device specific Block Diagrams) Table 1. CONFIGURATIONS Device Feedback From NB2308AI1 Bank A or Bank B NB2308AI1H Bank A or Bank B NB2308AI2 Bank ...
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Table 3. PIN DESCRIPTION Pin # Pin Name 1 REF (Note 3) 2 CLKA1 (Note 4) 3 CLKA2 (Note GND 6 CLKB1 (Note 4) 7 CLKB2 (Note (Note (Note ...
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Table 4. MAXIMUM RATINGS Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Maximum Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (per MIL--STD--883, Method 3015) Stresses exceeding Maximum Ratings may ...
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Table 7. SWITCHING CHARACTERISTICS Parameter Description t Output Frequency 1 t Duty Cycle = ( 100 (all devices) t Output Rise Time 3 (--1, --2, --3, --4) Output Rise Time (--1H, --5H) t ...
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Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. 1500 1000 500 0 --500 --1000 --1500 --30 --25 --20 --15 --10 -- OUTPUT LOAD DIFFERENCE: FBK LOAD -- ...
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V CLKOUT DD OUTPUTS 0 0.1 mF GND GND Figure 9. Test Circuit #1 PLL MUX REF S2 SELECT INPUT DECODING S1 Figure 11. NB2308AI1 and NB2308AI1H TEST CIRCUITS 0 LOAD 0.1 mF For parameter ...
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MUX PLL REF S2 SELECT INPUT DECODING ÷2 S1 Figure 13. NB2308AI3 REF S2 S1 BLOCK DIAGRAMS FBK CLKA1 ÷2 CLKA2 CLKA3 REF CLKA4 S2 SELECT INPUT S1 CLKB1 CLKB2 CLKB3 CLKB4 MUX PLL ÷2 SELECT INPUT DECODING Figure ...
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... NB2308AI1DR2G 2308AI1G NB2308AI1HDG 2308AI1HG NB2308AI1HDR2G 2308AI1HG NB2308AI1DTG 2308 AI1 NB2308AI1DTR2G 2308 AI1 NB2308AI1HDTG 2308 AI1H NB2308AI1HDTR2G 2308 AI1H NB2308AI2DG 2308AI2G NB2308AI2DR2G 2308AI2G NB2308AI2DTG 2308 AI2 NB2308AI2DTR2G 2308 AI2 NB2308AI2HDG 2308AI2HG NB2308AI2HDR2G 2308AI2HG NB2308AI2HDTG 2308 AI2H NB2308AI2HDTR2G 2308 AI2H NB2308AI3DG 2308AI3G NB2308AI3DR2G ...
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ORDERING INFORMATION Device Marking NB2308AI5HDG 2308AI5HG NB2308AI5HDR2G 2308AI5HG NB2308AI5HDTG 2308 AI5H NB2308AI5HDTR2G 2308 AI5H †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe- cifications Brochure, BRD8011/D. Operating ...
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... L PIN 1 IDENT. 1 0.15 (0.006 - 0.10 (0.004) - -T- - SEATING D PLANE 16X 0.36 *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP- -16 CASE 948F--01 ISSUE SECTION - 0.25 (0.010 ...
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... *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “ ...