SI5368B-B-GQ Silicon Laboratories Inc, SI5368B-B-GQ Datasheet - Page 62

• Manufacturer Part Number: SI5368B-B-GQ
• Description: IC ANY-RATE MULTI/ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5368B-B-GQ

• Number Of Circuits: 1
• Package / Case: 100-TQFP, 100-VQFP
• Pll: Yes with Bypass
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 4:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 808MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 1.62 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 808MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 1417 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.62 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5368
Reset value = 0000 0000
62
Register 133.
Name
Type
Bit
7:0
Bit
1
0
ALIGN_ERR
ALIGN_ERR
LOL_FLG
Name
D7
[8,8]
[7:0]
LOL_FLG.
PLL Loss of Lock Flag.
0: PLL locked
1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing
location to 0.
ALIGN_ERR [8:0].
Indicates the magnitude of the deviation of the input to output frame sync phase
alignment from the ideal value set in the FSYNC_SKEW[16:0] registers. The alignment
error is given in units of tCKOUT_2.
If the alignment error exceeds 255 fCKOUT_2 clock cycles, ALIGN_ERR[7:0] limits to its
maximum value (11111111). The polarity of the phase deviation (leading or lagging) is
given by the ALIGN_ERR[8] bit.
00000000=0
11111111=255
ALIGN_ERR [7:0].
See Register 132.
D6
D5
Preliminary Rev. 0.41
ALIGN_ERR [7:0]
D4
R
Function
D3
D2
D1
D0