SI5318-G-BC Silicon Laboratories Inc, SI5318-G-BC Datasheet - Page 14

• Manufacturer Part Number: SI5318-G-BC
• Description: IC MULTIPLIER SONET/SDH 63CBGA
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5318-G-BC

• Package / Case: 63-CBGA
• Pll: Yes
• Input: LVTTL
• Output: LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 173MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 173MHz
• Operating Supply Voltage: 3.3 V
• Supply Current: 140 mA
• Operating Temperature Range: - 55 C to + 150 C
• Mounting Style: SMD/SMT
• Operating Frequency: 622 MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1183

Si5318
2. Functional Description
The Si5318 is a high-performance precision clock
multiplication and clock generation device. This device
accepts a clock input in the 19, 39, 78, or 155 MHz
range, attenuates significant amounts of jitter, and
generates a clock output in the 19 or 155 MHz range.
The Si5318 employs Silicon Laboratories DSPLL
technology to provide excellent jitter performance while
minimizing
maximizing flexibility and ease-of-use. The Si5318
DSPLL phase locks to the input clock signal, attenuates
jitter, and multiplies the clock frequency to generate the
device
DSPLL loop bandwidth is user-selectable, allowing the
Si5318 jitter performance to be optimized for different
applications. The Si5318 can produce a clock output
with jitter generation as low as 1.0 ps
making the device an ideal solution for clock
multiplication in SONET/SDH systems.
The Si5318 monitors the clock input signal for loss-of-
signal, and provides a loss-of-signal (LOS) alarm when
missing pulses are detected. The Si5318 provides a
digital hold capability to continue generation of a stable
output clock when the input reference is lost.
2.1. DSPLL
The Si5318 phase-locked loop (PLL) uses Silicon
Laboratories' DSPLL technology to eliminate jitter,
noise, and the need for external loop filter components
found in traditional PLL implementations. This is
achieved by using a digital signal processing (DSP)
algorithm to replace the loop filter commonly found in
analog PLL designs. This algorithm processes the
phase detector error term and generates a digital
control value to adjust the frequency of the voltage-
controlled oscillator (VCO). The technology produces a
low phase noise clock with less jitter than is generated
using traditional methods. See Figure 4 for an example
phase noise plot. In addition, because external loop
filter components are not required, sensitive noise entry
points are eliminated, making the DSPLL less
susceptible to board-level noise sources.
14
SONET/SDH-compliant
the
®
external
component
clock
RMS
(see Table 4),
output.
count
The
and
Rev. 1.0
®
This digital technology also allows for highly stable and
consistent operation over all process, temperature, and
voltage variations.
2.1.1. Selectable Loop Filter Bandwidth
The digital nature of the DSPLL loop filter allows control
of the loop filter parameters without the need to change
external components. The Si5318 provides the user
with up to eight user-selectable loop bandwidth settings
for different system requirements. The base loop
bandwidth is selected using the BWSEL [1:0] and
DBLBW = 0 pins. When DBLBW is driven high, the
bandwidth selected on the BWSEL[1:0] pins is doubled.
(See Table 7.)
When DBLBW is asserted, the Si5318 shows improved
jitter generation performance. DBLBW function is
defined only when hitless recovery from digital hold is
disabled. Therefore, when DBLBW is high, the user
must also drive FXDDELAY high for proper operation.
2.2. Clock Input and Output Rate Selection
The Si5318 provides a 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, or 8x
clock frequency multiplication function. Output rates
vary in accordance with the input clock rate. The
multiplication factor is configured by selecting the input
and output clock frequency ranges for the device.
The Si5318 accepts an input clock in the 19, 39, 78, or
155 MHz frequency range. The input frequency range is
selected
INFRQSEL[2:0] settings and associated output clock
rates are given in Table 8.
The Si5318 DSPLL phase locks to the clock input signal
to generate an internal VCO frequency that is a multiple
of the input clock frequency. The internal VCO
frequency is divided down to produce a clock output in
the 19 or 155 MHz frequency range. The clock output
range
(FRQSEL[1:0]) pins. The FRQSEL[1:0] settings and
associated output clock rates are given in Table 9.
The Si5318 clock input frequencies are variable within
the range specified in Table 3 on page 7. The output
rates scale accordingly. When a 19.44 MHz input clock
is used, the clock output frequency is 19.44 or
155.52 MHz.
is
using
selected
the
using
INFRQSEL[2:0]
the
Frequency
pins.
Select
The