LMX2541SQ2060E/NOPB National Semiconductor, LMX2541SQ2060E/NOPB Datasheet - Page 53

• Manufacturer Part Number: LMX2541SQ2060E/NOPB
• Description: IC PLL FREQ SYNTH W/VCO 36LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of LMX2541SQ2060E/NOPB

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 2.24GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-LLP
• Frequency-max: 2.24GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2541SQ2060E

Sub-Fractional Spur Offset
Frequencies vs. Modulator Order
and Fractional Denominator Factors
Impact of VCO_DIV on Fractional spurs
Because the fractional and sub-fractional spur levels do not
depend on output frequency, there is a big benefit to division.
In general, every factor of 2 gives a 6 dB improvement to
fractional spurs. Also, since the spur offset frequency is not
divided, the channel spacing at the VCO can be also in-
creased to improve the spurs. However, if the on-chip VCO is
used, crosstalk can cause spurs at a frequency of f
f
tector frequency and VCO_DIV = 2. If the VCO is at 3000.1
MHz and divided by 2 to get 1500.05 MHz, there will be a spur
at an offset of 50 kHz (1500.05 MHz mod 50 MHz). However,
if the VCO frequency is at 3050.1 MHz, the output will be at
1525.05 MHz, but the spur will be at a much farther offset that
can easily be filtered by the loop filter of 25.05 MHz (1525.05
MHz mod 50 MHz).
3.4 PLL PHASE NOISE
Disregarding the impact of reference oscillator noise, loop fil-
ter resistor thermal noise, and loop filter shaping, the phase
noise of the PLL can be decomposed into three components:
flicker noise, flat noise, and fractional noise. These noise
sources add in an RMS sense to produce the total PLL noise.
In other words:.
L
10·log(10(
The preceding table shows which factors of offset frequency
(f), VCO frequency (f
charge pump gain (K
can potentially influence each phase noise component. The
fractional settings include the fraction, modulator order, and
dithering.
For the flat noise and flicker noise, it is possible to normalize
each of these noise sources into a single index. By normaliz-
PD
Modulator
2nd Order
Modulator
Modulator
Modulator
3rd Order
1st Order
4th Order
PLL
ORDER
Integer
. Consider the following example of a 50 MHz phase de-
Mode
(f) =
L
L
PLL_fractional
L
PLL_flicker
Symbol
PLL_flat
L
PLL_flat
No Factor
of 2 or 3
(f)
(f)
None
None
None
None
None
(f) / 10 )
(f)
Fractional Denominator Factors
PD
+ 10(
VCO
), and the fractional settings (FRAC)
Yes
Yes
2 but not 3
No
Factor of
), phase detector frequency (f
Potential Influencing Factors
f
L
None
None
Fch/2
Fch/2
Fch/4
PLL_flicker
f
Yes
Yes
VCO
No
(f) / 10 )
3 but not 2
Factor of
Fch/3
Fch/3
None
None
None
Yes
Yes
+ 10(
f
No
PD
L
PLL_fractional
K
Yes
Yes
No
PD
Factor of
2 and 3
Fch/12
RFout
Fch/2
Fch/6
None
None
(f) / 10 )
FRAC
Yes
No
No
mod
PD
),
53
ing these noise sources to an index, it makes it possible to
calculate the flicker and flat noise for an arbitrary condition.
These indices are reported in the electrical characteristics
section and in the typical performance curves.
The flat noise is dependent on the PLL N divider value (N)
and the phase detector frequency (f
ized phase noise ( LN
noise can also depend on the charge pump gain as well. In
order to make an accurate measurement of just the flat noise
component, the offset frequency must be chosen sufficiently
smaller then the loop bandwidth of the PLL, and yet large
enough to avoid a substantial noise contribution from the ref-
erence and PLL flicker noise. This becomes easier to mea-
sure for lower phase detector frequencies.
The flicker noise, also known as 1/f noise, can be normalized
to 1 GHz carrier frequency and 10 kHz offset, LN
kHz). Flicker noise can dominate at low offsets from the car-
rier and has a 10 dB/decade slope and improves with higher
charge pump currents and at higher offset frequencies . To
accurately measure the flicker noise it is important to use a
high phase detector frequency and a clean crystal to make it
such that this measurement is on the 10 dB/decade slope
close to the carrier. L
ence oscillator performance if a low power or noisy source is
used.
An alternative way to interpret the flicker noise is the 1/f noise
corner, f
flat noise and flicker noise are equal. This corner frequency
changes as a function of the phase detector frequency and
can be related to the flat and flicker noise indices as shown
below.
f
Based on the values for LNPLL_flicker(10 kHz) and
LNPLL_flat(1Hz) as reported in the electrical specifications,
the corner frequency can be calculated. For example, one of
the plots in the typical performance characteristics shows the
phase noise with a 100 MHz phase detector frequency and
32X charge pump gain. In this case, this corner frequency
works out to be 0.000123 × 100 MHz = 12.3 kHz.
For integer mode or a first order modulator, there is no frac-
tional noise (disregarding fractional spurs). For higher order
modulators, the fractional engine may or may not add signif-
icant phase noise depending on the fraction and choice of
dithering.
corner
K
32X
Component
1X
L
PD
L
PLL_flicker
PLL_flat
Noise
= 10
LN
corner
-116.0 dBc/Hz
-124.5 dBc/Hz
PLL_flicker(10 kHz)
(f)
( (LN
(f)
. This would be the offset frequency where the
PLL_flicker
LN
LN
(10 kHz)
Index
(1 Hz)
(10 kHz) - LN
PLL_flicker
PLL_flat
PLL_flat(1 Hz)
PLL_flicker
-220.8 dBc/Hz 0.000302 × f
-225.4 dBc/Hz 0.000123 × f
LN
(f) can be masked by the refer-
PLL_flat
PLL_flat(1 Hz)
- 10·log(10 kHz / f) + 20·log
). The 1 Hz normalized phase
+ 20·log(N) + 10·log(f
(1 Hz) - 140) / 10 )
LN
PD
( f
) and the 1 Hz Normal-
PLL_flicker
Relationship
L
LN
L
VCO
PLL_flicker
PLL_flat
PLL_flat(1 Hz)
/ 1 GHz )
(10 kHz)
(f) =
× f
(f) =
www.national.com
f
PLL_flicker
corner
PD
PD
)
PD
PD
(10