CS82C84AZ Intersil, CS82C84AZ Datasheet - Page 7

• Manufacturer Part Number: CS82C84AZ
• Description: IC DRIVER CLOCK GENERATOR 20PLCC
• Manufacturer: Intersil
• Type: Clock Generator, Clock Synchronizer, Fanout Distributionr

Specifications of CS82C84AZ

• Pll: No
• Input: TTL
• Output: TTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 25MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-PLCC
• Frequency-max: 25MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC Electrical Specifications
NOTES:
1. Tested as follows: f = 2.4MHz, V
2. Tested using EFI or X1 input pin.
3. Setup and hold necessary only to guarantee recognition at next clock.
4. Applies only to T2 states.
5. Applies only to T3 TW states.
6. Tested with EFI input frequency = 4.2MHz.
TIMING REQUIREMENTS
TIMING RESPONSES
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
between 0.4V and V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
TEHEL
TELEH
TELEL
TR2VCL
TR1VCH
TR1VCL
TCLR1X
TAYVCL
TCLAYX
TA1VR1V
TCLA1X
TYHEH
TEHYL
TYHYL
TI1HCL
TCLI1H
TCLCL
TCHCL
TCLCH
TCH1CH2
TCL2CL1
TPHPL
TPLPH
TRYLCL
TRYHCH
TCLIL
TCLPH
TCLPL
TOLCH
TOLCL
SYMBOL
CC
-0.4V. Input rise and fall times driven at 1ns/V. V
External Frequency HIGH Time
External Frequency LOW Time
EFI Period
XTAL Frequency
RDY1, RDY2 Active Setup to CLK
RDY1, RDY2 Active Setup to CLK
RDY1, RDY2 Inactive Setup to CLK
RDY1, RDY2 Hold to CLK
ASYNC Setup to CLK
ASYNC Hold to CLK
AEN1, AEN2 Setup to RDY1, RDY2
AEN1, AEN2 Hold to CLK
CSYNC Setup to EFI
CSYNC Hold to EFI
CSYNC Width
RES Setup to CLK
RES Hold to CLK
CLK Cycle Period
CLK HIGH Time
CLK LOW Time
CLK Rise or Fall Time
PCLK HIGH Time
PCLK LOW Time
Ready Inactive to CLK (See Note 4)
Ready Active to CLK (See Note 3)
CLK to Reset Delay
CLK to PCLK HIGH Delay
CLK to PCLK LOW Delay
OSC to CLK HIGH Delay
OSC to CLK LOW Delay
7
IH
= 2.6V, V
V
T
T
T
A
A
A
CC
= 0
= -40
= -55
PARAMETER
= +5V± 10%,
o
IL
C to +70
o
o
= 0.4V, C
C to +85
C to +125
o
C (C82C84A),
L
o
C (I82C84A),
o
= 50pF, V
C (M82C84A)
82C84A
82C84A
OH
≥ 1.5V, V
IL
(2/3 TCLCL) -15.0
(2/3 TCLCL) -15.0
(1/3 TCLCL) +2.0
≤ V
TCLCL-20
TCLCL-20
2 TELEL
IL
MIN
OL
(max) - 0.4V for CSYNC pin. V
125
2.4
13
13
36
35
35
35
50
15
20
20
65
20
-8
-5
0
0
0
2
-
-
-
-
≤ 1.5V, unless otherwise specified. RES and F/C must switch
LIMITS
MAX
25
10
40
22
22
22
35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CC
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
= 4.5V and 5.5V.
90%-90% V
10%-10% V
Note 2
ASYNC = HIGH
ASYNC = LOW
Note 3
Note 3
Note 6
Note 6
Note 6
1.0V to 3.0V
Note 6
Note 6
Note 4
Note 5
CONDITIONS
(NOTE 1)
TEST
December 6, 2005
IN
IN
FN2974.3