ICS527R-01 IDT, Integrated Device Technology Inc, ICS527R-01 Datasheet - Page 9

• Manufacturer Part Number: ICS527R-01
• Description: IC CLOCK SLICER ZD BUFFER 28SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of ICS527R-01

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 160MHz
• Number Of Elements: 1
• Supply Current: 8mA
• Pll Input Freq (min): 600KHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: QSOP
• Output Frequency Range: 4 to 160MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Pin Count: 28
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 527R-01

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 9
ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
AC Electrical Characteristics
External Components
Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85 C
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.
The ICS527-01 requires two 0.01 µF decoupling capacitors to be connected between VDD and GND, one
on each side of the chip. They must be connected close to the device to minimize lead inductance. No
external power supply filtering is required for this device. A 33 series terminating resistor should be used
on the CLK1 and CLK2 output pins.
Input Frequency
Output Frequency, CLK1
CLK1 Frequency for Correct
SYNC Operation
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Power Down Time, PDTS low to
clocks tri-stated
Power Up Time, PDTS high to
clocks stable
Absolute Clock Period Jitter
One sigma Clock Period Jitter
Skew of Output Clocks
Input Capacitance
Input to Output Skew
Device to Device Skew
Parameter
Symbol
F
t
t
C
F
t
t
t
OUT
OR
OD
t
t
OF
t
IO
IO
ja
js
pi
IN
IN
0 to +70 C
-40 to +85 C
0.8 to 2.0 V
2.0 to 0.8 V
Measured at VDD/2,
C
Deviation from mean
CLK1 to CLK2, Note 1
ICLK to FBIN, Note 1
Common ICLK, at FBIN
L
=15 pF
Conditions
Min.
-250
-250
0.6
45
4
4
ZDB AND MULTIPLIER/DIVIDER
Typ.
± 90
50
40
1
1
4
0
ICS527-01
Max.
200
160
140
250
500
250
66
55
50
10
REV G 051310
Units
MHz
MHz
MHz
MHz
ms
pF
ns
ns
ns
ps
ps
ps
ps
ps
%