IDT2305-1DC IDT, Integrated Device Technology Inc, IDT2305-1DC Datasheet
IDT2305-1DC
Specifications of IDT2305-1DC
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IDT2305-1DC Summary of contents
Page 1
... All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2305 enters power down. In this mode, the device will draw less than 25 and the PLL is not running, resulting in a significant reduction of power ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER PIN CONFIGURATION 1 REF CLK2 2 3 CLK1 GND 4 SOIC/TSSOP TOP VIEW APPLICATIONS: • SDRAM • Telecom • Datacom • PC Motherboards/Workstations • Critical Path Delay Designs PIN DESCRIPTION Pin Name Pin Number REF 1 (1) CLK2 2 (2) CLK1 ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER OPERATING CONDITIONS - COMMERCIAL Symbol Parameter V Supply Voltage DD T Operating Temperature (Ambient Temperature Load Capacitance < 100MHz L Load Capacitance 100MHz - 133MHz C Input Capacitance IN DC ELECTRICAL CHARACTERISTICS - COMMERCIAL Symbol Parameter V Input LOW Voltage Level IL V Input HIGH Voltage Level ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER SWITCHING CHARACTERISTICS (2305-1H) - COMMERCIAL Symbol Parameter t Output Frequency 1 ÷ t Duty Cycle = Duty Cycle = t ÷ Rise Time 3 t Fall Time 4 t Output to Output Skew 5 t Delay, REF Rising Edge to CLKOUT Rising Edge 6 t Device-to-Device Skew 7 t Output Slew Rate ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER SWITCHING CHARACTERISTICS (2305-1) - INDUSTRIAL Symbol Parameter t Output Frequency 1 Duty Cycle = t ÷ Rise Time 3 t Fall Time 4 t Output to Output Skew 5 t Delay, REF Rising Edge to CLKOUT Rising Edge 6 t Device-to-Device Skew 7 t Cycle-to-Cycle Jitter PLL Lock Time ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER ZERO DELAY AND SKEW CONTROL All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other outputs that can adjust the Input-Output (I/O) Delay ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER SWITCHING WAVEFORMS t1 t2 1.4V 1.4V Duty Cycle Timing 2V 0.8V 0.8V 2V Output t3 All Outputs Rise/Fall Time TEST CIRCUITS V DD 0.1 F OUTPUTS V DD 0.1 F GND GND Test Circuit 1 (all Parameters Except t8) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Output 1 ...
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... Number of Loaded Outputs NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V data is calculated from nCVf, where CORE V = Supply Voltage (V Frequency (Hz)) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AND I TRENDS FOR IDT2305-1 (1) ( 33M 66M H z 100M 3.5 3 -40C ...
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... Num ber of Loaded Outputs NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current Number of outputs Capacitance load per output (F Supply Voltage (V Frequency (Hz)) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AND I TRENDS FOR IDT2305-1H (1) ( 33M Hz ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER PACKAGE OUTLINE AND PACKAGE DIMENSIONS - SOIC N INDEX AREA 150 mil (Narrow Body) SOIC In Millimeters COMMON DIMENSIONS SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 0.19 0. SEE VARIATIONS E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER PACKAGE OUTLINE AND PACKAGE DIMENSIONS - TSSOP COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 11 ...
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... IDT2305 3.3V ZERO DELAY CLOCK BUFFER ORDERING INFORMATION IDT XXXXX XX Package Device Type Ordering Code 2305-1DCG8 (tape and reel) 2305-1DCG 2305-1DCGI8 (tape and reel) 2305-1DCGI 2305-1HDCG 2305-1HDCG8 (tape and reel) 2305-1HDCGI 2305-1HDCGI8 (tape and reel) 2305-1PGGI 2305-1PGG (G=Lead-free, RoHS compliant) CORPORATE HEADQUARTERS ...