SKY72301-22 Skyworks Solutions Inc, SKY72301-22 Datasheet - Page 4

• Manufacturer Part Number: SKY72301-22
• Description: IC SYNTHESIZER 1GHZ 28-EPTSSOP
• Manufacturer: Skyworks Solutions Inc
• Type: Fractional N Synthesizerr

Specifications of SKY72301-22

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• Frequency-max: 1GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 863-1078-2

DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Serial Interface Operation
The serial interface consists of three signals: Clock (pin 1), Data
(pin 27) and CS (pin 28). The Clock signal controls data on the two
serial data lines (Data and CS). The Data pin bits shift into a
temporary register on the rising edge of Clock. The CS line allows
individual selection transfers that synchronize and sample the
information of slave devices on the same bus.
Figure 3 functionally depicts how a serial transfer takes place.
A serial transfer is initiated when a microcontroller or
microprocessor forces the CS line to a low state. This is followed
immediately by an address/data stream sent to the Data pin that
coincides with the rising edges of the clock presented on the
Clock line.
Each rising edge of the Clock signal shifts in one bit of data on the
Data line into a shift register. At the same time, one bit of data is
shifted out of the Mux_out pin (if the serial bit stream is selected)
at each falling edge of Clock. To load any of the registers, 16 bits
of address or data must be presented to the Data line with the
LSB last while the CS signal is low. If the CS signal is low for
more than 16 clock cycles, only the last address or data bits are
used to load the registers.
If the CS signal is brought to a high state before the 13
edge, the bit stream is assumed to be modulation data samples.
In this case, it is assumed that no address bits are present and
that all the bits in the stream should be loaded into the
Modulation Data Register.
4
Clock
Data
CS
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
September 11, 2009 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200706C
X
A3
A2
A1
A0 D11 D10 D9
Figure 3. Serial Transfer Timing Diagram
th
Clock
D8
Register Programming
Register programming equations, described in this section, use
the following variables and constants:
N
N
N
divider
dividend When in 18-bit mode, this is the 18-bit signed input
F
F
D7
VCO
div_ref
fractional
integer
reg
D6
Desired VCO division ratio in fractional-N applications.
This is a real number and can be interpreted as the
reference frequency (F
the resulting frequency is equal to the desired VCO
frequency.
Desired VCO division ratio in integer-N applications.
This number is an integer and can be interpreted as
the reference frequency (F
the resulting frequency is equal to the desired VCO
frequency.
Nine-bit unsigned input value to the divider ranging
from 0 to 511 (integer-N mode) and from 6 to 505
(fractional-N mode).
This constant equals 262144 when the
is in 18-bit mode, and 1024 when the
in 10-bit mode.
value to the
–131072 to +131071 and providing 262144 steps,
each step equal to F
When in 10-bit mode, this is the 10-bit signed input
value to the
–512 to +511 and providing 1024 steps, each step
equal to Fdiv_ref/2
Desired VCO frequency (either F
Divided reference frequency presented to the phase
detector (either F
D5
D4
D3
D2
modulator, ranging from
modulator, ranging from
ref_main
10
div_ref
Hz.
D1
ref
or F
) multiplying factor such that
/2
ref
18
D0
ref_aux
) multiplying factor so that
Hz.
Last
).
vco_main
XXX
C1413
or F
vco_aux
modulator is
modulator
).