DS1085LZ-25+ Maxim Integrated Products, DS1085LZ-25+ Datasheet - Page 19

• Manufacturer Part Number: DS1085LZ-25+
• Description: IC ECONOSCILL FREQ SYNTH 8SOIC
• Manufacturer: Maxim Integrated Products
• Series: EconOscillator™r
• Type: Frequency Synthesizerr

Specifications of DS1085LZ-25+

• Pll: No
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 66MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 66MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7) DAC and OFFSET register settings must be configured to maintain the clock frequency within this
8) Frequency settles faster for small charges in value. During a change, the frequency changes smoothly
9) This indicates the time taken between power-up and the outputs becoming active. An on-chip delay is
10) Output voltage swings can be impaired at high frequencies combined with high-output loading.
11) After this period, the first clock pulse is generated.
12) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
13) The maximum t
14) A fast mode device can be used in a standard mode system, but the requirement t
15) C
16) EEPROM write begins after a STOP condition occurs.
17) Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr
+125 ° C bake, 168hr 85 ° C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5 ° C peak) followed by 1000hr max
V
ATM Steam/Unbiased Autoclave.
Figure 5. MASTER FREQUENCY TEMPERATURE VARIATION
CC
range. Correct operation of the device is not guaranteed if these limits are exceeded.
from the original value to the new value.
intentionally introduced to allow the oscillator to stabilize. t
clock cycles and hence depends on the programmed clock frequency.
V
SCL signal.
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line at least t
released.
biased 125 ° C HTOL, 1000 temperature cycles at -55 ° C to +125 ° C, 96hr 130 ° C/85%RH/5.5V HAST and 168hr 121 ° C/2
B
IH MIN
—total capacitance of one bus line in picofarads; timing referenced to 0.9V
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
HD:DAT
need only be met if the device does not stretch the LOW period (t
-0.50
-1.00
-1.50
-2.00
2.00
1.50
1.00
0.50
0.00
R MAX
33
MASTER FREQUENCY TEMPERATURE
MAST ER OSCILLAT OR FREQUENCY (MHz)
+ t
41.25
SU:DAT
VARIATION
19 of 21
= 1000ns + 250ns = 1250ns before the SCL line is
49.5
57.75
stab
66
is equivalent to approximately 8000
CC
and 0.1V
SU:DAT
> 250ns must
CC
LOW
.
) of the