CY23EP09SXC-1 Cypress Semiconductor Corp, CY23EP09SXC-1 Datasheet

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CY23EP09SXC-1

Manufacturer Part Number
CY23EP09SXC-1
Description
IC CLK ZDB 9OUT 220MHZ 16SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Zero Delay Bufferr
Datasheet

Specifications of CY23EP09SXC-1

Number Of Circuits
1
Package / Case
16-SOIC (3.9mm Width)
Pll
Yes with Bypass
Input
LVCMOS, LVTTL
Output
LVCMOS
Ratio - Input:output
1:9
Differential - Input:output
No/No
Frequency - Max
133MHz, 167MHz
Divider/multiplier
No/No
Voltage - Supply
2.5V, 3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
220MHz
Maximum Input Frequency
167 MHz
Minimum Input Frequency
10 MHz
Output Frequency Range
10 MHz to 167 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V, 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Cypress Semiconductor Corporation
Document #: 38-07760 Rev. *B
Features
REF
• 10 MHz to 220 MHz maximum operating range
• Zero input-output propagation delay, adjustable by
• Multiple low-skew outputs
• 25 ps typical cycle-to-cycle jitter
• 15 ps typical period jitter
• Standard and High drive strength options
• Available in space-saving 16-pin 150-mil SOIC or
• 3.3V or 2.5V operation
• Industrial temperature available
Block Diagram
loading on CLKOUT pin
— 45 ps typical output-output skew
— One input drives nine outputs, grouped as 4 + 4 + 1
4.4-mm TSSOP packages
S2
S1
PLL
Select Input
Decoding
2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output
MUX
198 Champion Court
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Functional Description
The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed
to distribute high-speed clocks and is available in a 16-pin
SOIC or TSSOP package. The -1H version operates up to 220
(200) MHz frequencies at 3.3V (2.5V), and has higher drive
than the -1 devices. All parts have on-chip PLLs that lock to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
There are two banks of four outputs each, which can be
controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 2. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The PLL enters a power-down mode when there are no rising
edges on the REF input (less than ~2 MHz). In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25 µA of current draw.
In the special case when S2:S1 is 1:0, the PLL is bypassed
and REF is output from DC to the maximum allowable
frequency. The part behaves like a non-zero delay buffer in this
mode, and the outputs are not tri-stated.
The CY23EP09 is available in different configurations, as
shown in the Ordering Information table. The CY23EP09-1 is
the base part. The CY23EP09-1H is the high-drive version of
the -1, and its rise and fall times are much faster than the -1.
These parts are not intended for 5V input-tolerant applications
CLKA1
CLKA2
CLKB1
CLKB2
San Jose
GND
Pin Configuration
REF
V
S2
DD
,
1
2
3
4
5
6
7
8
Top View
CA 95134-1709
Zero Delay Buffer
15
14
13
12
11
10
16
9
Revised October 5, 2005
CLKOUT
CLKA4
CLKA3
V
GND
CLKB4
CLKB3
S1
DD
CY23EP09
408-943-2600
[+] Feedback

Related parts for CY23EP09SXC-1

CY23EP09SXC-1 Summary of contents

Page 1

... PLL REF S2 Select Input Decoding S1 Cypress Semiconductor Corporation Document #: 38-07760 Rev. *B Functional Description The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The -1H version operates up to 220 (200) MHz frequencies at 3.3V (2.5V), and has higher drive than the -1 devices ...

Page 2

Pin Definition Pin Signal [1] 1 REF [2] 2 CLKA1 [2] 3 CLKA2 GND [2] 6 CLKB1 [2] 7 CLKB2 [ [ [2] 10 CLKB3 [2] 11 CLKB4 12 GND 13 V ...

Page 3

Absolute Maximum Conditions Supply Voltage to Ground Potential ................. –0.5V to 4.6V DC Input Voltage...................................... V Operating Conditions Parameter V 3.3V Supply Voltage DD3.3 V 2.5V Supply Voltage DD2.5 T Operating Temperature (Ambient Temperature)—Commercial A Operating Temperature (Ambient Temperature)—Industrial [5] ...

Page 4

DC Electrical Specifications Parameter Description V Supply Voltage DD V Input LOW Voltage IL V Input HIGH Voltage IH I Input Leakage Current IL I Input HIGH Current IH V Output LOW Voltage OL V Output HIGH Voltage OH ...

Page 5

AC Electrical Specifications Parameter Description [9] t PLL Lock Time LOCK [9,10] T Cycle-to-cycle Jitter, Peak 3.3V supply, >66 MHz, <15 pF JCC [9,10] T Period Jitter, Peak PER Note: 10. Typical jitter is measured at 3.3V ...

Page 6

Switching Waveforms (continued OUTPUT OUTPUT t V INPUT CLKOUT t 6 Any output, Part Any output, Part Test Circuits Test Circuit # CLK 0.1 µ F OUTPUTS V DD ...

Page 7

Supplemental Parametric Information 1200 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -1200 -20 Figure 1. 2.5V Typical Room Temperature Graph for REF Input to CLKA/CLKB Delay versus Loading Difference between CLKOUT and CLKA/CLKB. Data is shown ...

Page 8

Figure 3. 3.6V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature. Note that the 30-pF data above 100 MHz is beyond the data sheet specification of 22 pF. ...

Page 9

Figure 5. Typical 3.3V Measured Cycle-to-cycle Jitter at 29°C, versus Frequency, Drive Strength, and Loading ...

Page 10

Standard Drive 2.5V, Standard Drive 2.5V, High Drive 2.5V, High Drive -100 -100 -110 -110 -120 -120 -130 -130 100 MHz 100 MHz -140 -140 1.E+01 1.E+01 1.E+02 1.E+02 -90 -90 -100 -100 -110 -110 -120 -120 ...

Page 11

... SOIC – Tape and Reel CY23EP09SXI-1 16-pin 150-mil SOIC – CY23EP09SXI-1T 16-pin 150-mil SOIC – Tape and Reel CY23EP09SXC-1H 16-pin 150-mil SOIC CY23EP09SXC-1HT 16-pin 150-mil SOIC – Tape and Reel CY23EP09SXI-1H 16-pin 150-mil SOIC CY23EP09SXI-1HT 16-pin 150-mil SOIC – Tape and Reel CY23EP09ZXC-1H 16-pin 4 ...

Page 12

... Document #: 38-07760 Rev. *B © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 13

Document History Page Document Title: CY23EP09 2.5V or 3.3V, 10-220-MHz, Low Jitter, 9-Output Zero Delay Buffer Document Number: 38-07760 REV. ECN NO. Issue Date ** 345446 See ECN *A 355777 See ECN *B 401036 See ECN Document #: 38-07760 Rev. ...

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