ICS650R-01I IDT, Integrated Device Technology Inc, ICS650R-01I Datasheet - Page 3

• Manufacturer Part Number: ICS650R-01I
• Description: IC CLK SYNTHESIZER 20-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizerr

Specifications of ICS650R-01I

• Pll: Yes with Bypass
• Input: Clock, Crystal
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 66.67MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Frequency-max: 67MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 650R-01I

External Components
The ICS650-01 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50 trace (a commonly used trace
impedance) place a 33 resistor in series with the clock line,
IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE
Number
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
Pin
11
12
13
14
15
16
17
18
19
20
14.318M
PCLK1
PCLK3
PCLK2
PSEL0
PSEL1
Name
ASEL
GND
VDD
Pin
OE
Output
Output
Output
Output
Power
Power
Type
Input
Input
Input
Input
Pin
Output enable. Tri-states all outputs when low.
PCLK output number 1 per table above.
14.31818 MHz Buffered reference clock output.
Connect to ground.
ACLK select pin. Determines frequency of Audio clock per table above.
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
PCLK output number 3 per table above.
PCLK output number 2 per table above.
Processor select pin #0. Determines frequencies on PCLKs 1-4 per table
above.
Processor select pin #1. Determines frequencies on PCLKs 1-4 per table
above.
3
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20 .
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant, 300 ppm or better (to
meet Ethernet specs). Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
In the equation, C
crystal with a 16 pF load capacitance, two 8 pF capacitors
should be used. If a clock input is used, drive it into X1 and
leave X2 unconnected.
Pin Description
Crystal caps (pF) = (C
L
is the crystal load capacitance. So, for a
L
- 12) x 2
ICS650-01
CLOCK SYNTHESIZER
REV H 051310