CY2308SXC-1H Cypress Semiconductor Corp, CY2308SXC-1H Datasheet - Page 6

• Manufacturer Part Number: CY2308SXC-1H
• Description: IC CLK ZDB 8OUT 133MHZ 16SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY2308SXC-1H

• Number Of Circuits: 1
• Package / Case: 16-SOIC (3.9mm Width)
• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 133.3MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 133MHz
• Output Frequency Range: 10 MHz to 133.3 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2197-5; CY2308SXC-1H

Switching Characteristics for Commercial Temperature Devices
Document Number: 38-07146 Rev. *L
Notes
t
t
t
t
t
t
t
t
t
t
t
t
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t
t
10. All parameters are specified with loaded outputs.
11. Parameter is guaranteed by design and characterization. Not 100% tested in production.
12. All parameters are specified with loaded outputs.
PD
PD
3
3
3
4
4
4
5
6
7
8
J
J
LOCK
Parameter
[9]
Duty cycle
(–1, –2, –3, –4, –1H, –5H)
Duty cycle
(–1, –2, –3, –4, –1H, –5H)
Rise time
(–1, –2, –3, –4)
Rise time
(–1, –2, –3, –4)
Rise time
(–1H, –5H)
Fall time
(–1, –2, –3, –4)
Fall time
(–1, –2, –3, –4)
Fall time
(–1H, –5H)
Output to output skew on same
Bank (–1, –2, –3, –4)
Output to output skew (–1H,
–5H)
Output Bank A to output Bank
B skew (–1, –4, –5H)
Output Bank A to output Bank
B skew (–2, –3)
Delay, REF rising edge to FBK
rising edge
Device to device skew
Output slew rate
Cycle to cycle Jitter
(–1, –1H, –4, –5H)
Cycle to cycle Jitter
(–2, –3)
PLL lock time
[10, 12]
[10, 12]
[10, 12]
[10, 12]
[10, 12]
[10, 12]
[10, 12]
[10, 12]
[10, 12]
Name
[10, 12]
[10, 12]
= t
= t
[10, 12]
[10, 12]
2
2
[10, 12]
t
t
[10, 12]
1
1
Measured at 1.4 V, F
66.66 MHz, 30 pF load
Measured at 1.4 V, F
50 MHz, 15 pF load
Measured between 0.8 V and
2.0 V, 30 pF load
Measured between 0.8 V and
2.0 V, 15 pF load
Measured between 0.8 V and
2.0 V, 30 pF load
Measured between 0.8 V and
2.0 V, 30 pF load
Measured between 0.8 V and
2.0 V, 15 pF load
Measured between 0.8 V and
2.0 V, 30 pF load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
Measured at V
pins of devices
Measured between 0.8 V and
2.0 V on –1H, –5H device using
Test Circuit 2
Measured at 66.67 MHz,
loaded outputs, 15 pF load
Measured at 66.67 MHz,
loaded outputs, 30 pF load
Measured at 133.3 MHz,
loaded outputs, 15 pF load
Measured at 66.67 MHz,
loaded outputs, 30 pF load
Measured at 66.67 MHz,
loaded outputs, 15 pF load
Stable power supply, valid
clocks presented on REF and
FBK pins
Test Conditions
DD
DD
/2 on the FBK
/2
OUT
OUT
=
<
40.0
45.0
Min
–
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
(continued)
Typ.
50.0
50.0
75
–
–
–
–
–
–
–
–
–
–
0
0
–
–
–
–
–
–
±250
Max
60.0
55.0
2.20
1.50
1.50
2.20
1.50
1.25
200
200
200
400
700
200
200
100
400
400
1.0
CY2308
Page 6 of 17
Unit
V/ns
ms
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%
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