CY25562SXC Cypress Semiconductor Corp, CY25562SXC Datasheet - Page 3

• Manufacturer Part Number: CY25562SXC
• Description: IC CLOCK GEN 3.3V SS 8-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock/Frequency Synthesizer, Frequency Modulator, Spread Spectrum Clock Generatorr

Specifications of CY25562SXC

• Number Of Circuits: 1
• Package / Case: 8-SOIC (3.9mm Width)
• Pll: Yes
• Input: Clock, Crystal
• Output: Clock
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 200 MHz
• Minimum Input Frequency: 50 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2223-5; CY25562SXC

Table 1. Frequency and Spread Percentage Selection (Center Spread)
Tri-level Logic
With binary logic, four states can be programmed with two control lines, whereas tri-level logic can program nine logic states using
two control lines. Tri-level logic in CY25562 is implemented by defining a third logic state in addition to the standard logic “1” and “0.”
Pins six and seven of CY25562 recognize a logic state by the voltage applied to the respective pin. These states are defined as “0”
(low), “M” (middle), and “1” (one). Each of these states have a defined voltage range that is interpreted by CY25562 as “0”, “M,” or “1”
logic state. Refer to
6 and pin 7, which produce the default “M” state. Pins six and/or seven can be tied directly to ground or V
“1” state, respectively. See the following examples:
SSCG Theory of Operation
CY25562 is a PLL-type clock generator using a proprietary
Cypress design to modulate the reference clock. By precisely
controlling the bandwidth of the output clock, CY25562 becomes
a low-EMI clock generator. The theory and detailed operation of
CY25562 is discussed in the following sections.
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50 percent. Because of this 50/50 duty cycle,
digital clocks generate most of their harmonic energy in the odd
Document Number: 38-07392 Rev. *D
F r e q u e n c y
F r e q u e n c y
S1 = "0" (GND)
SSCC = "1"
1 0 0 – 1 2 0
S0 = "M" (N/C)
1 3 0 - 1 4 0
1 4 0 - 1 5 0
1 5 0 - 1 6 0
1 6 0 - 1 7 0
1 7 0 - 1 8 0
1 8 0 - 1 9 0
1 9 0 - 2 0 0
1 2 0 - 1 3 0
8 0 - 1 0 0
5 0 - 6 0
6 0 - 7 0
7 0 - 8 0
CY25562
( M H z )
( M H z )
I n p u t
I n p u t
Table 2
7
6
5
S0
VDD
S1
S 1 = M
S 0 = M
S 0 = M
S 1 = 1
for voltage ranges for each logic state. CY25562 has two equal value resistors connected internally to pin
( % )
( % )
4 . 3
4 . 0
3 . 8
3 . 5
3 . 0
2 . 7
2 . 6
2 . 6
2 . 5
2 . 4
2 . 4
2 . 3
2 . 3
1 0 0 – 2 0 0 M H z ( H i g h R a n g e )
5 0 – 1 0 0 M H z ( L o w R a n g e )
S 1 = M
S 0 = 0
S 1 = 0
S 0 = 1
( % )
( % )
3 . 9
3 . 6
3 . 4
3 . 1
2 . 4
2 . 1
2 . 0
2 . 0
1 . 8
1 . 8
1 . 8
1 . 7
1 . 6
Figure 2. Tri-level Logic Example
S1 = "0" (GND)
SSCC = "1"
CY25562
S0 = "1"
S 1 = 1
S 0 = 0
S 1 = 1
S 0 = 1
( % )
( % )
3 . 3
3 . 1
2 . 9
2 . 7
1 . 6
1 . 4
1 . 3
1 . 3
1 . 2
1 . 2
1 . 2
1 . 1
1 . 1
7
6
5
harmonics, that is; third, fifth, seventh, etc. The amount of energy
contained in the fundamental and odd harmonics can be reduced
by increasing the bandwidth of the fundamental clock frequency.
Conventional digital clocks have a very high Q factor; all the
energy at that frequency is concentrated in a very narrow
bandwidth, and consequently, higher energy peaks. Regulatory
agencies test electronic equipment by the amount of peak
energy radiated from the equipment. By reducing the peak
energy at the fundamental and harmonic frequencies, the
equipment under test satisfies agency requirements for EMI.
Conventional methods of reducing EMI use shielding, filtering,
multi-layer PCBs, etc. CY25562 reduces the peak energy in the
clock by increasing the clock bandwidth, thus lowering the Q.
S0
VDD
S1
S 1 = M
S 1 = 0
S 0 = 0
S 0 = 1
( % )
( % )
2 . 9
2 . 6
2 . 5
2 . 2
1 . 3
1 . 1
1 . 1
1 . 1
1 . 0
1 . 0
1 . 0
0 . 9
0 . 9
VDD
S 0 = M
S 1 = 0
( % )
2 . 7
2 . 5
2 . 4
2 . 1
SSCC = "1"
CY25562
S0 = "1"
S1 = "1"
S e l e c t t h e
F r e q u e n c y a n d
C e n t e r S p r e a d %
d e s i r e d a n d t h e n
s e t S 1 , S 0 a s
i n d i c a t e d .
S e l e c t t h e
F r e q u e n c y a n d
C e n t e r S p r e a d %
d e s i r e d a n d t h e n
s e t S 1 , S 0 a s
i n d i c a t e d .
DD
to program a logic “0” or
7
6
5
S1
CY25562
S0
Page 3 of 8
VDD
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