ADF4113HVBRUZ Analog Devices Inc, ADF4113HVBRUZ Datasheet - Page 15

• Manufacturer Part Number: ADF4113HVBRUZ
• Description: IC CHARGE PUMP HV SYNTH 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4113HVBRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Pll Type: Frequency Synthesis
• Frequency: 4GHz
• Supply Current: 16mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4113HVEB1Z - BOARD EVALUATION FOR ADF4113HVEVAL-ADF4113EBZ2 - BOARD EVAL FOR ADF4113 1750MHZEVAL-ADF4113EBZ1 - BOARD EVAL FOR ADF4113EVAL-ADF411XEBZ1 - BOARD EVAL FOR ADF411X NO CHIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

APPLICATIONS
USING A DIGITIAL-TO-ANALOG CONVERTER TO
DRIVE THE R
A digital-to-analog converter (DAC) can be used to drive the
R
over the charge pump current (I
wideband applications where the sensitivity of the VCO varies
over the tuning range. To compensate for this, I
to maintain good phase margin and ensure loop stability. See
Figure 23 for this configuration.
INTERFACING
The ADF4113HV has a simple SPI®-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When latch enable (LE) goes high, the 24 bits that have
been clocked into the input register on each rising edge of CLK
are transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 6 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device
is 833 kHz, or one update every 1.2 μs. This rate is more than
adequate for systems that have typical lock times in the
hundreds of microseconds.
ADuC812 Interface
Figure 24 shows the interface between the ADF4113HV and the
ADuC812 MicroConverter®. Because the
an 8051 core, this interface can be used with any 8051-based
SET
pin of the ADF4113HV, thus increasing the level of control
SET
PIN
FREF
IN
2.7kΩ
SPI-COMPATIBLE SERIAL BUS
CP
). This can be advantageous in
8
1
CE
CLK
DATA
LE
V-OUT DAC
REF
R
AD5320
ADF4113HV
SET
12-BIT
IN
ADuC812
Figure 23. Driving the R
MUXOUT
RF
RF
CP
IN
IN
CP
can be varied
A
B
14
2
6
5
is based on
100pF
LOCK
DETECT
100pF
NOTES
1. POWER SUPPLY CONNECTIONS AND DECOUPLING
Rev. A | Page 15 of 20
CAPACITORS ARE OMITTED FOR CLARITY.
SET
Pin with a Digital-to-Analog Converter
51Ω
FILTER
LOOP
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4113HV needs
a 24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
has been written, the LE input should be brought high to
complete the transfer.
I/O port lines on the ADuC812 are also used to control power-
down (CE input), and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When the ADuC812 is operating in the SPI master mode, the
maximum SCLOCK rate of the ADuC812 is 4 MHz. This
means that the maximum rate at which the output frequency
can be changed is 166 kHz.
ADuC812
INPUT OUTPUT
GND
VCO
Figure 24. ADuC812 to ADF4113HV Interface
I/O PORTS
SCLOCK
MOSI
100pF
100pF
18Ω
18Ω
18Ω
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
RF
OUT
ADF4113HV
ADF4113HV