SKY72302-21 Skyworks Solutions Inc, SKY72302-21 Datasheet - Page 8

• Manufacturer Part Number: SKY72302-21
• Description: IC SYNTHESIZER 6.1GHZ 28-EPTSSOP
• Manufacturer: Skyworks Solutions Inc
• Type: Fractional N Synthesizerr

Specifications of SKY72302-21

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 6.1GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• Frequency-max: 6.1GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 863-1079-2

DATA SHEET • SKY72302-21 FREQUENCY SYNTHESIZER
Normal Register Write. A normal 16-bit serial interface write
occurs when the CS signal is 16 clock cycles wide. The
corresponding 16-bit modulation data is simultaneously
presented to the Data pin. The content of the Modulation Data
Register is passed to the modulation unit at the next falling edge
of the divided main VCO frequency (F
Short CS Through Data Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide. The corresponding modulation data (2
to 12 bits) is simultaneously presented to the Data pin. The Data
pin is the default pin used to enter modulation data directly in the
Modulation Data Register with shortened CS strobes.
This method of data entry eliminates the register address
overhead on the serial interface. All serial interface bits are re-
synchronized internally at the reference oscillator frequency. The
content of the Modulation Data Register is passed to the
modulation unit at the next falling edge of the divided main VCO
frequency (F
Short CS Through Mod_in Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide. The corresponding modulation data (2
to 12 bits) is simultaneously presented to the Mod_in pin, an
alternate pin used to enter modulation data directly into the
Modulation Data Register with shortened CS strobes.
8
pd_main
Case 1: To achieve a desired F
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
).
September 9, 2009 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 101216L
divide ratio is 32, the reference frequency (F
frequency divide ratio of 2 provides a reference frequency of 8 MHz. Therefore:
The value to be programmed in the Auxiliary Divider Register is:
Summary:
· · Auxiliary Divide Register = 0 0001 0010
N
N
integer
reg
= N
= 50 – 32
= 18 (decimal)
= 000010010 (binary)
pd_main
integer
=
=
=
).
vco_aux
Figure 5. Integer-N Applications: Sample Calculation
F
F
– 32
vco_aux
div_ref
400
50
8
frequency of 400 MHz using a crystal frequency of 16 MHz. Since the minimum
div_ref
) must be a maximum of 12.5 MHz. Choosing a reference
This mode is selected through the Modulation Control Register.
This method of data entry also eliminates the register address
overhead on the serial interface and allows a different device than
the one controlling the channel selection to enter the modulation
data (e.g., a microcontroller for channel selection and a digital
signal processor for modulation data).
All serial interface bits are internally re-synchronized at the
reference oscillator frequency and the content of the Modulation
Data Register is passed to the modulation unit at the next falling
edge of the divided main VCO frequency (F
Modulation data samples in the Modulation Data Register can be
from 2 to 12 bits long, and enable the user to select how many
distinct frequency steps are to be used for the desired modulation
scheme.
The user can also control the frequency deviation through the
modulation data magnitude offset in the Modulation Control
Register. This allows shifting of the modulation data to
accomplish a 2
NOTE: The programmable range of –0.5 to +0.5 of the main
the sum of the dividend and the modulation data conform
to:
modulator can be exceeded up to the condition where
. 0
m
5625
multiplication of frequency deviation.
(
N
mod
dividend
)
pd_main
. 0
).
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C1416