CY29949AXI Cypress Semiconductor Corp, CY29949AXI Datasheet - Page 2

• Manufacturer Part Number: CY29949AXI
• Description: IC CLK BUFF 1:15 200MHZ 52TQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of CY29949AXI

• Package / Case: 52-TQFP
• Number Of Circuits: 1
• Ratio - Input:output: 1:15
• Differential - Input:output: Yes/Yes
• Input: LVCMOS, LVPECL, LVTTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 200MHz
• Voltage - Supply: 2.375 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Clock Inputs: 3
• Output Logic Level: LVCMOS, LVTTL
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Temperature: + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Configuration
Pin Description
Note
Document #: 38-07289 Rev. *E
6
7
4, 5
49, 51
42, 44, 46
31, 33, 35, 37
16, 18, 20, 22, 24, 28 QD(5:0)
9, 10, 11, 12
2
8
1
17, 21, 25, 32, 36,
41, 45, 50
3
13, 15, 19, 23, 29,
30, 34, 38, 43, 47,
48, 52
14, 26, 27, 39, 40,
1. PD = internal pull-down, PU = internal pull-up.
Pin
PECL_CLK
PECL_CLK#
TCLK(0,1)
QA(1,0)
QB(2:0)
QC(3:0)
DSEL(A:D)
TCLK_SEL
PCLK_SEL
MR/OE#
VDDC
VDD
VSS
NC
Name
PECL_CLK#
PECL_CLK
TCLK_SEL
PCLK_SEL
MR/OE#
VDDC
VDDC
VDDC
VDDC
DSELA
DSELB
DSELC
DSELD
TCLK0
TCLK1
VDD
PWR
VSS
Figure 1. Pin Diagram - CY29949
1
2
3
4
5
6
7
8
9
10
11
12
13
52 51 50 49 48 47 46 45 44 43 42 41 40
14 15 16 17 18 19 20 21 22 23 24 25 26
I/O
I, PD PECL Input Clock
I, PU PECL Input Clock
I, PU External Reference/Test Clock Input
I, PD Divider Select Inputs. When HIGH, selects ÷2 input divider. When LOW,
I, PD TCLK Select Input. When LOW, TCLK0 clock is selected and when
I, PD PECL Select Input. When HIGH, PECL clock is selected and when LOW
I, PD Output Enable Input. When asserted LOW, the outputs are enabled and
O
O
O
O
[1]
CY29949
Clock Outputs
Clock Outputs
Clock Outputs
Clock Outputs
selects ÷1 input divider.
HIGH TCLK1 is selected.
TCLK(0,1) is selected
when asserted HIGH, internal flip-flops are reset and the outputs are
three-stated. If more than one bank is used in /2 mode, a reset must be
performed (MR/OE# asserted high) after power up to ensure that all
internal flip-flops are set to the same state.
2.5V or 3.3V Power Supply for Output Clock Buffers
2.5V or 3.3V Power Supply
Common Ground
Not Connected
39
38
37
36
35
34
33
32
31
30
29
28
27
NC
VSS
QC0
VDDC
QC1
VSS
QC2
VDDC
QC3
VSS
VSS
QD5
NC
Description
CY29949
Page 2 of 7
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