MC100EP14DTG ON Semiconductor, MC100EP14DTG Datasheet
MC100EP14DTG
Specifications of MC100EP14DTG
Available stocks
Related parts for MC100EP14DTG
MC100EP14DTG Summary of contents
Page 1
MC100EP14 3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100EP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential ...
Page 2
WARNING: All V Figure 1. TSSOP−20 (Top View) and Logic Diagram Table 1. PIN DESCRIPTION Pin Function CLK0*, CLK0** ECL/PECL/HSTL CLK Input CLK1*, CLK1** ECL/PECL/HSTL CLK Input Q0:4, Q0:4 ECL/PECL ...
Page 3
Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see ...
Page 4
Table 5. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...
Page 5
Table 7. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...
Page 6
... Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100EP14DT MC100EP14DTG MC100EP14DTR2 MC100EP14DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ...
Page 7
Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...
Page 8
... −V− 0.100 (0.004) −T− SEATING PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE Í Í Í Í ...
Page 9
... Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...