NB7V585MMNR4G ON Semiconductor, NB7V585MMNR4G Datasheet - Page 5
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NB7V585MMNR4G
Manufacturer Part Number
NB7V585MMNR4G
Description
IC CLK/DATA BUFFER/XLATOR 32-QFN
Manufacturer
ON Semiconductor
Series
GigaComm™r
Type
Fanout Buffer (Distribution), Multiplexer , Translator, Datar
Datasheet
1.NB7V585MMNR4G.pdf
(8 pages)
Specifications of NB7V585MMNR4G
Number Of Circuits
1
Ratio - Input:output
2:6
Differential - Input:output
Yes/Yes
Input
CML, LVDS, LVPECL
Output
CML
Frequency - Max
7GHz
Voltage - Supply
1.71 V ~ 2.625 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TFQFN Exposed Pad
Frequency-max
7GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NB7V585MMNR4G
Manufacturer:
ON
Quantity:
5
Company:
Part Number:
NB7V585MMNR4G
Manufacturer:
ON Semiconductor
Quantity:
430
Part Number:
NB7V585MMNR4G
Manufacturer:
ON/安森美
Quantity:
20 000
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
11. Measured using a 400 mV source, 50% duty cycle clock source. All outputs must be loaded with external 50 W to V
12. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
15. Input and output voltage swing is a single−ended measurement operating in differential mode.
Table 6. AC CHARACTERISTICS
f
f
V
t
t
t
t
t
V
t
Symbol
MAX
DATAMAX
PLH
PLH
SKEW
DC
JITTER
r
, t
OUTPP
INPP
(20% − 80%).
the delays are measured from cross−point of the inputs to the crosspoint of the outputs.
f
, t
TC
PHL
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
450
400
350
300
250
200
150
Figure 2. Output Voltage Amplitude (V
Frequency (f
0
Maximum Input Clock Frequency, V
Maximum Operating Input Data Rate (PRBS23)
Output Voltage Amplitude (See Figures 4, Note 15)
Propagation Delay to Output Differential @ 1 GHz,
Measured at Differential Crosspoint
Propagation Delay Temperature Coefficient
Output − Output Skew (Within Device) (Note 12)
Device − Device Skew (t
Output Clock Duty Cycle (Reference Duty Cycle = 50%) f
Output Random Jitter (RJ) (Note 13)
Deterministic Jitter (DJ) (Note 14)
Input Voltage Swing (Differential Configuration) (Note 15)
Output Rise/Fall Times @ 1 GHz (20% − 80%)
1.0
f
out
, CLOCK OUTPUT FREQUENCY (GHz)
2.0
in
) at Ambient Temperature (Typical)
3.0
pd
4.0
V
Max − t
CC
Characteristic
= 1.8 V $5% or 2.5 V $5%, GND = 0 V, T
5.0
pdmin
OUTPP
)
OUTPP
6.0
w 200 mV
http://onsemi.com
) vs. Input
7.0
IN
8.0
5
x
f
f
f
f
in
in
in
/IN
in
in
v 10 Gbps
v 4.0 GHz
v 6.0 GHz
v 4.0 GHz
v 6.0 GHz
x
SEL to Q
to Q
Q
n
n
, Q
/Q
n
n
n
V
IN
IN
Tx
x
x
A
= −40°C to 85°C (Note 11)
50 W
50 W
Figure 3. Input Structure
Min
250
200
125
100
6.0
10
45
Typ
400
325
175
200
100
7.0
0.2
50
50
V
CC
CC
. Input edge rates 40 ps
1200
Max
250
300
0.8
30
50
55
10
65
ps pk−pk
ps rms
Gbps
Unit
GHz
fs/°C
mV
mV
ps
ps
ps
%