MAX9312ECJ+ Maxim Integrated Products, MAX9312ECJ+ Datasheet - Page 4

• Manufacturer Part Number: MAX9312ECJ+
• Description: IC DVR CLK/DATA DUAL 1:5 32LQFP
• Manufacturer: Maxim Integrated Products
• Type: Fanout Buffer (Distribution), Datar

Specifications of MAX9312ECJ+

• Number Of Circuits: 2
• Ratio - Input:output: 1:5
• Differential - Input:output: Yes/Yes
• Input: HSTL, LVECL, LVPECL
• Output: LVECL, LVPECL
• Frequency - Max: 3GHz
• Voltage - Supply: 2.25 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 3GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC ELECTRICAL CHARACTERISTICS
(V
(20% to 80%), V
erwise noted. Typical values are at V
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Note 2: Measurements are made with the device in thermal equilibrium.
Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 4: Single-ended input operation using V
Note 5: DC parameters production tested at T
Note 6: Use V
Note 7: All pins open except V
Note 8: Guaranteed by design and characterization limits are set at ±6 sigma.
Note 9: Measured between outputs on the same part at the signal crossing points for a same-edge transition.
Note 10: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 11: Device jitter added to the input signal.
4
PARAMETER
Differential Input-
to-Output Delay
Output-to-Output
Skew (Note 9)
Part-to-Part Skew
(Note 10)
Added Random
Jitter (Note 11)
Added
Deterministic
Jitter (Note 11)
Switching
Frequency
Outp ut Ri se/Fal l
Ti m e ( 20% to 80%)
CC
_______________________________________________________________________________________
- V
EE
3.8V for the MAX9314.
ature range.
= +2.25V to +3.8V, outputs loaded with 50Ω ±1% to V
BB
IHD
only for inputs that are on the same device as the V
= V
SYM B O L
t
t
t
t
PLHD
SKOO
t
f
PHLD
SKPP
EE
MAX
R
t
t
RJ
DJ
, t
+ 1.2V to V
F
,
CC
Figure 2
f
clock pattern
f
clock pattern
3Gbps,
2
V
cl ock p atter n, Fi g ur e 2
V
cl ock p atter n, Fi g ur e 2
Figure 2
IN
IN
23
OH
OH
CONDITIONS
= 1.5GHz
= 3.0GHz
and V
-1 PRBS pattern
CC
- V
- V
CC
OL
OL
- V
, V
EE
≥ 300m V ,
≥ 500m V ,
EE
ILD
.
= 3.3V, V
BB
= V
A
= +25°C. Guaranteed by design and characterization over the full operating temper-
is limited to V
EE
to V
IHD
MIN
100
220
1.5
CC
= V
- 0.15V, V
CC
-40°C
CC
TYP
112
321
1.2
3.0
30
1.2
80
12
- 1V, V
- V
CC
EE
BB
IHD
MAX
- 2V, input frequency = 1.5GHz, input transition time = 125ps
160
140
ILD
380
2.6
2.5
46
95
= 3.0V to 3.8V for the MAX9312 and V
reference.
- V
= V
ILD
CC
MIN
100
220
1.5
= 0.15V to the smaller of 3V or V
- 1.5V.) (Note 8)
+25°C
TYP
116
312
1.2
3.0
1.2
30
80
12
MAX
410
190
140
2.6
2.5
46
95
MIN
260
100
1.5
+85°C
TYP
322
121
1.2
1.2
3.0
10
30
80
CC
CC
- V
- V
MAX
EE
400
140
140
2.5
2.6
35
95
EE
= 2.7V to
, unless oth-
UNITS
(pk-pk)
(RMS)
GHz
ps
ps
ps
ps
ps
ps