NB6L611MNR2G ON Semiconductor, NB6L611MNR2G Datasheet

IC CLK/FANOUT BUFF 1:2 16-QFN

NB6L611MNR2G

Manufacturer Part Number
NB6L611MNR2G
Description
IC CLK/FANOUT BUFF 1:2 16-QFN
Manufacturer
ON Semiconductor
Series
ECLinPS MAX™r
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of NB6L611MNR2G

Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
Yes/Yes
Input
CML, LVCMOS, LVDS, LVPECL, LVTTL
Output
LVPECL
Frequency - Max
4GHz
Voltage - Supply
2.375 V ~ 3.63 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TFQFN Exposed Pad
Frequency-max
4GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
NB6L611MNR2G
NB6L611MNR2GOSTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NB6L611MNR2G
Manufacturer:
ON Semiconductor
Quantity:
2 100
Part Number:
NB6L611MNR2G
Manufacturer:
ON/安森美
Quantity:
20 000
NB6L611
2.5V / 3.3V 1:2 Differential
LVPECL Clock / Data Fanout
Buffer
Multi−Level Inputs with Internal Termination
Description
differential inputs incorporate internal 50 W termination resistors that
are accessed through the VTD pins and will accept LVPECL, CML,
LVDS, LVCMOS or LVTTL logic levels.
capacitor−coupled differential or single−ended input signals. When
used, decouple V
sourcing or sinking to 0.5 mA. When used, decouple V
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
performance clock and data management products.
Features
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 4
The NB6L611 is a differential 1:2 clock or data fanout buffer. The
T h e V
The device is housed in a small 3x3 mm 16 pin QFN package.
The NB6L611 is a member of the ECLinPS MAX™ family of high
EP, and SG Devices
Input Clock Frequency > 4.0 GHz
280 ps Typical Propagation Delay
100 ps Typical Rise and Fall Times
0.5 ps maximum RMS Clock Jitter
Differential LVPECL Outputs, 780 mV Amplitude, typical
LVPECL Operating Range: V
NECL Operating Range: V
Internal Input Termination Resistors, 50 W
V
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
REFAC
R E FA C
Reference Output Voltage
REFAC
REFAC
r e f e r e n c e o u t p u t c a n b e u s e d t o r e b i a s
output should be left open.
with a 0.01 mF capacitor and limit current
CC
CC
= 0 V with V
= 2.375 V to 3.63 V with V
EE
= −2.375 V to −3.63 V
REFAC
1
with a
EE
= 0 V
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
VREFAC
*For additional marking information, refer to
VTD
VTD
Application Note AND8002/D.
1
Figure 1. Simplified Logic Diagram
A
L
Y
W
G
(Note: Microdot may be in either location)
D
D
ORDERING INFORMATION
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
http://onsemi.com
CASE 485G
MN SUFFIX
QFN−16
Publication Order Number:
1
DIAGRAM*
16
MARKING
ALYWG
NB6L
NB6L611/D
611
G
Q0
Q0
Q1
Q1

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NB6L611MNR2G Summary of contents

Page 1

NB6L611 2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer Multi−Level Inputs with Internal Termination Description The NB6L611 is a differential 1:2 clock or data fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are ...

Page 2

Table 1. PIN DESCRIPTION Pin Name I/O 1 VTD − ECL, CML, LVCMOS, LVDS, LVTTL Input 3 D ECL, CML, LVCMOS, LVDS, LVTTL Input 4 VTD − − REFAC 7 V − EE ...

Page 3

Table 2. ATTRIBUTES ESD Protection Moisture Sensitivity Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply CC V Negative ...

Page 4

Table 4. DC CHARACTERISTICS, Multi−Level Inputs −3. −40°C to +85°C A Symbol Characteristic POWER SUPPLY CURRENT I Power Supply Current (Inputs and Outputs Open) CC LVPECL OUTPUTS (Notes 4 and 5) V Output HIGH Voltage OH V ...

Page 5

Table 5. AC CHARACTERISTICS −40°C to +85°C; (Note 10) A Symbol V Output Voltage Amplitude (@ V OUTPP (Note 14) (See Figure 3) t Propagation Delay PD t Duty Cycle Skew (Note 11) SKEW Within Device Skew ...

Page 6

Figure 4. Typical Phase Noise Plot 311.04 MHz carrier Figure 6. Typical Phase Noise Plot GHz carrier The above phase noise plots captured using Agilent E5052A show additive phase noise of the NB6L611 ...

Page 7

Figure 9. Differential Input Driven Single−Ended D D Figure 11. Differential Inputs Driven Differentially IHD(MAX) V ILD(MAX) V IHD CMR ID V ILD ...

Page 8

LVPECL − Driver Figure 15. LVPECL Interface V CC CML Driver V EE Figure 17. Standard 50 W ...

Page 9

... Figure 20. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device NB6L611MNG NB6L611MNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ ...

Page 10

... E2 e 3.25 0.128 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6,362,644. There may be other patents pending. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2− ...

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