CY2DL814ZXC Cypress Semiconductor Corp, CY2DL814ZXC Datasheet - Page 3

• Manufacturer Part Number: CY2DL814ZXC
• Description: IC CLK FANOUT BUFFER 1:4 16TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: ComLink™r
• Type: Fanout Buffer (Distribution)r

Specifications of CY2DL814ZXC

• Package / Case: 16-TSSOP
• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/Yes
• Input: LVDS, LVPECL, LVTTL
• Output: LVDS
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 400MHz
• Number Of Outputs: 8
• Max Input Freq: 400 MHz
• Propagation Delay (max): 4 ns
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Power Dissipation: 750 mW
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07057 Rev. *B
Table 3. Input Receiver Configuration for Differential or LVTTL/LVCMOS
Table 4. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal
Table 5. Power Supply Characteristics
Table 6. D.C Electrical Characteristics: 3.3V–LVDS Input
Table 7. D.C Electrical Characteristics: 3.3V–LVPECL Input
I
I
V
V
V
V
I
I
I
Parameter
V
V
I
I
I
CCD
C
IH
IL
I
Parameter
IH
IL
I
ID
IC
IH
IL
ID
CM
Ground
Ground
Parameter
V
V
CC
CC
Binary Value
CONFIG
Magnitude of Differential Input Voltage
Common-mode of Differential Input Voltage IV
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Pin 2
Input Condition
Differential Input Voltage p-p
Common-mode Voltage
Input High Current
Input Low Current
Input High Current
1
0
Dynamic Power Supply Current
Total Power Supply Current
Description
Description
IN+ Pin 6
IN+ Pin 6
IN+ Pin 6
IN+ Pin 6
IN– Pin 7
IN– Pin 7
IN– Pin 7
IN– Pin 7
Description
LVTTL in LVCMOS
LVDS
LVPECL
Input Receiver Family
Guaranteed Logic High Level
Guaranteed Logic Low Level
V
V
V
DD
DD
DD
= Max.
= Max.
= Max., V
Guaranteed Logic High Level
V
V
V
DD
DD
DD
LVTTL/LVCMOS Input Logic
= Max.
= Max., V
= Max.
Input Logic
V
V
Input toggling 50% Duty Cycle,
Outputs Open
Input toggling 50% Duty Cycle,
Outputs Open
fL=100 MHz
IN
DD
DD
Input
Input
Input
Input
= V
ID
= Max.
= Max.
IN
I (min. and max.)
DD
Single-ended, Non-inverting, Inverting, Void of Bias Resistors
Low-voltage Differential Signaling
Low-voltage Pseudo (Positive) Emitter Coupled Logic
Test Conditions
Conditions
Conditions
= V
(max.)
DD
(Max.)
V
V
Config/Cntrl Pins
IN
IN
= V
= V
V
Input Receiver Type
V
Output Logic Q Pins, Q1A or Q1
IN
IN
DD
SS
= V
= V
Min.
DD
SS
Min.
1.65
400
ComLink™ Series
Invert
Invert
IVIDI/2
True
True
Typ.
1.5
Min.
90
100
2
Typ.
±10
±10
Max.
2.4–(IVIDI/2)
Typ.
CY2DL814
100
2.0
±10
±10
2600
Max.
2.25
±20
±20
±20
Page 3 of 8
Max. Unit
600
±20
±20
±20
mA/MHz
0.8
Unit
mA
Unit
mV
µA
µA
µA
V
mV
µA
µA
µA
V
V
V