SY100EP14AUKG Micrel Inc, SY100EP14AUKG Datasheet - Page 3

• Manufacturer Part Number: SY100EP14AUKG
• Description: IC FANOUT BUFFER PECL 20-TSSOP
• Manufacturer: Micrel Inc
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of SY100EP14AUKG

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: ECL, HSTL, LVPECL
• Output: ECL
• Frequency - Max: 2GHz
• Voltage - Supply: 2.375 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3697-5; SY100EP14AUKG

Pin Description
Truth Table
Note:
Function Table
Micrel, Inc.
June 2010
Pin Number
CLK0
1, 2, 3, 4
5, 6, 7, 8
1.
13, 14
16, 17
18, 20
H
L
X
X
X
9, 10
19
12
15
11
On next negative transition of CLK0 or CLK1.
CLK_SEL
0
1
CLK1
Q0, /Q0, Q1, /Q1
Q2, /Q2, Q3, /Q3
H
X
X
X
L
CLK0, /CLK0
CLK1, /CLK1
Pin Name
Q4, /Q4
VCC
SEL
VBB
VEE
/EN
CLK_SEL
H
H
X
L
L
Pin Function
LVPECL, LVECL, HSTL Clock or Data Inputs. Internal 75kΩ pull-down resistors on CLK0, CLK1,
and internal 75kΩ pull-up and 75kΩ pull-down resistors on /CLK0, /CLK1. For single-ended
applications, connect signal into CLK0 and/or CLK1 inputs. /CLK0, /CLK1 default condition is
V
LVPECL/LVECL Differential Outputs: Terminate with 50Ω to V
applications, /Q0 to /Q4 terminate the unused output with 50Ω to V
LVPECL/LVECL compatible synchronous enable: When /EN goes HIGH, the Q
and /Q
Default state is LOW when left floating. The internal latch is clocked on the falling edge of the
input clock (CLK0, CLK1).
LVPECL/LVECL compatible 2:1 MUX input signal select: When SEL is LOW, CLK0 input pair is
selected. When SEL is HIGH, CLK1 input pair is selected. Includes a 75kΩ pull-down. Default
state is LOW and CLK0 is selected.
Output Reference Voltage: Equal to V
or AC-coupled applications. For single-ended LVPECL and LVECL applications, bypass with a
0.01µF to V
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors.
Negative Power Supply: LVPECL applications, connect to GND.
CC
/2 when left floating. CLK0, CLK1 default condition is LOW when left floating.
CLK0, /CLK0
CLK1, /CLK1
Active Input
/EN
OUT
H
L
L
L
L
will go HIGH on the next LOW input clock transition. Includes a 75kΩ pull-down.
CC.
Max. sink/source current is 0.5mA.
Q
H
H
L
L
L
3
CC
-1.4V (approx.), and used for single-ended input signals
CC
-2V. For single-ended
CC
-2V.
[e-mail]
OUT
M9999-061110-A
SY100EP14AU
will go LOW