AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 38

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9511
Phase offsets may be related to degrees by calculating the phase
step for a particular divide ratio:
Using some of the same examples,
DELAY BLOCK
OUT4 (LVDS/CMOS) includes an analog delay element that
can be programmed (Register 34h to Register 36h) to give
variable time delays (ΔT) in the clock signal passing through
that output.
The amount of delay that can be used is determined by the
frequency of the clock being delayed. The amount of delay can
approach one-half cycle of the clock period. For example, for a
10 MHz clock, the delay can extend to the full 10 ns maximum
of which the delay element is capable. However, for a 100 MHz
clock (with 50% duty cycle), the maximum delay is less than
5 ns (or half of the period).
OUT4 allows a full-scale delay in the range 1 ns to 10 ns. The
full-scale delay is selected by choosing a combination of ramp
current and the number of capacitors by writing the appropriate
values into Register 35h. There are 32 fine delay settings for
each full scale, set by Register 36h.
CLOCK INPUT
DIV = 18
Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
Phase Step = 360°/(Divide Ratio) = 360°/DIV
DIV = 4
Phase Step = 360°/4 = 90°
Unique Phase Offsets in Degrees Are Phase = 0°, 90°,
DIV = 7
Phase Step = 360°/7 = 51.43°
Unique Phase Offsets in Degrees Are Phase = 0°, 51.43°,
11, 12, 13, 14, 15, 16, 17
180°, 270°
102.86°, 154.29°, 205.71°, 257.15°, 308.57°
∅SELECT
÷
N
Figure 40. Analog Delay (OUT4)
FULL-SCALE: 1ns TO 10ns
FINE DELAY ADJUST
OUT4 ONLY
(32 STEPS)
Δ
T
CMOS
LVDS
OUTPUT
DRIVER
Rev. A | Page 38 of 60
This path adds some jitter greater than that specified for the
nondelay outputs. This means that the delay function should be
used primarily for clocking digital chips, such as FPGA, ASIC,
DUC, and DDC, rather than for data converters. The jitter is
higher for long full scales (~10 ns). This is because the delay
block uses a ramp and trip points to create the variable delay. A
longer ramp means more noise may be introduced.
Calculating the Delay
The following values and equations are used to calculate the
delay of the delay block.
Value of Ramp Current Control Bits (Register 35h or Register 39h
<2:0>) = Iramp_bits
I
No. of Caps = No. of 0s + 1 in Ramp Control Capacitor
(Register 35h or Register 39h <5:3>), that is, 101 = 1 + 1 = 2; 110
= 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1)
Delay_Range (ns) = 200 × [(No. of Caps + 3)/(I
Delay_Full_Scale (ns) = Delay_Range + Offset
Fine_Adj = Value of Delay Fine Adjust (Register 36h or
Register 3Ah <5:1>), that is, 11111 = 31
Delay (ns) = Offset + Delay_Range × Fine_adj × (1/31)
OUTPUTS
The AD9511 offers three different output level choices:
LVPECL, LVDS, and CMOS. OUT0 to OUT2 are LVPECL only.
OUT3 and OUT4 can be selected as either LVDS or CMOS.
Each output can be enabled or turned off as needed to save
power.
The simplified equivalent circuit of the LVPECL outputs is
shown in Figure 41.
Offset
RAMP
(μA) = 200 × (Iramp_bits + 1)
( )
ns
Figure 41. LVPECL Output Simplified Equivalent Circuit
=
0.34
+
(
1600
GND
−
I
RAMP
)
×
3.3V
10
−
4
+
⎛
⎜
⎜
⎝
No.
OUT
OUTB
of
I
RAMP
RAMP
Caps
)] × 1.3286
−
1
⎞
× ⎟ ⎟
⎠
6